W79E532/W79L532
ISP Address Low Byte
Bit:
7
A7
Mnemonic: SFRAL
6
A6
5
A5
4
A4
3
A3
2
A2
1
A1
Address: ACh
0
A0
Low byte destination address for In System Programming operation. SFRAH and SFRAL address a
specific ROM byte for erasure, programming or read.
ISP Address High Byte
Bit:
7
A15
Mnemonic: SFRAH
6
A14
5
A13
4
A12
3
A11
2
A10
1
A9
Address: ADh
0
A8
High byte destination address for In System Programming operation. SFRAH and SFRAL address a
specific ROM byte for erasure, programming or read.
ISP Data Buffer
Bit:
7
D7
Mnemonic: SFRFD
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
Address: AEh
0
D0
In ISP mode, read/write a specific byte ROM content must go through SFRFD register.
ISP Operation Modes
Bit:
7
BANK
Mnemonic: SFRCN
6
WFWIN
5
NOE
4
NCE
3
CTRL3
2
CTRL2
1
CTRL1
0
CTRL0
Address: AFh
BANK: Select APFlash banks for ISP. Set it 1 access to APFlash1, clear it to APFlash0.
WFWIN: Destination ROM bank for programming, erasure and read. 0 = APFlashx, 1 = LDFlash.
NOE: Flash EPROM output enable.
NCE: Flash EPROM chip enable.
CTRL[3:0]: Mode Selection.
ISP Mode
Erase 4KB LDFlash
Erase 64K APFlash0
Erase 64K APFlash1
Program 4KB LDFlash
BANK
0
0
1
0
WFWIN
1
0
0
1
NOE
1
1
1
1
NCE
0
0
0
0
CTRL<3:0>
0010
0010
0010
0001
SFRAH,
SFRAL
X
X
X
Address in
SFRFD
X
X
X
Data in
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Publication Release Date: November 21, 2005
Revision A5