W79E532/W79L532
18.3.2 MOVX Characteristics Using Strech Memory Cycle
PARAMETER
SYMBOL
VARIABLE
CLOCK
MIN.
1.5t
CLCL
- 5
2.0t
CLCL
- 5
0.5t
CLCL
- 5
2.0t
CLCL
- 5
t
MCS
- 10
2.0t
CLCL
- 5
t
MCS
- 10
2.0t
CLCL
- 20
t
MCS
- 20
0
t
CLCL
- 5
2.0t
CLCL
- 5
2.5t
CLCL
- 5
t
MCS
+ 2t
CLCL
- 40
3.0t
CLCL
- 20
2.0t
CLCL
- 5
0.5t
CLCL
- 5
1.5t
CLCL
- 5
t
CLCL
- 5
2.0t
CLCL
- 5
1.5t
CLCL
- 5
2.5t
CLCL
- 5
-5
1.0t
CLCL
- 5
t
CLCL
- 5
2.0t
CLCL
- 5
0.5t
CLCL
- 5
0
1.0t
CLCL
- 5
10
1.0t
CLCL
+ 5
0.5t
CLCL
+ 5
1.5t
CLCL
+ 5
VARIABLE
CLOCK
MAX.
UNITS
STRECH
t
MCS
= 0
t
MCS
>0
Data Access ALE Pulse Width
Address Hold After ALE Low for
MOVX write
t
LLHL2
t
LLAX2
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV1
t
LLWL
nS
nS
nS
RD
Pulse Width
t
MCS
= 0
t
MCS
>0
t
MCS
= 0
t
MCS
>0
t
MCS
= 0
t
MCS
>0
WR
Pulse Width
RD
Low to Valid Data In
Data Hold after Read
Data Float after Read
nS
nS
nS
nS
t
MCS
= 0
t
MCS
>0
t
MCS
= 0
t
MCS
>0
t
MCS
= 0
t
MCS
>0
t
MCS
= 0
t
MCS
>0
t
MCS
= 0
t
MCS
>0
t
MCS
= 0
t
MCS
>0
t
MCS
= 0
t
MCS
>0
t
MCS
= 0
t
MCS
>0
ALE Low to Valid Data In
nS
Port 0 Address to Valid Data In
nS
ALE Low to
RD
or
WR
Low
Port 0 Address to
RD
or
WR
Low
Port 2 Address to
RD
or
WR
Low
Data Valid to WR Transition
nS
t
AVWL
nS
t
AVWL2
nS
t
QVWX
t
WHQX
t
RLAZ
t
WHLH
nS
Data Hold after Write
nS
nS
nS
RD
Low to Address Float
RD
or WR high to ALE high
t
MCS
= 0
t
MCS
>0
Note:
t
MCS
is a time period related to the Stretch memory cycle selection. The following table shows the time period of t
MCS
for each selection of the Stretch value.
- 65 -
Publication Release Date: November 21, 2005
Revision A5