W79E532/W79L532
18.3.4 Data Memory Read Cycle
ALE
t
LLDV
t
WHLH
PSEN
t
LLWL
t
LLAX1
t
RLRH
t
RLDV
RD
t
AVLL
t
AVWL1
t
RLAZ
t
RHDZ
t
RHDX
DATA
IN
ADDRESS
A0-A7
PORT 0
INSTRUCTION
IN
ADDRESS
A0-A7
t
AVDV1
t
AVDV2
PORT 2
ADDRESS A8-A15
18.3.5 Data Memory Write Cycle
ALE
t
WHLH
PSEN
t
LLWL
t
LLAX2
t
AVLL
t
WLWH
WR
t
AVWL1
t
QVWX
PORT 0
INSTRUCTION
IN
ADDRESS
A0-A7
DATA OUT
t
WHQX
ADDRESS
A0-A7
t
AVDV2
PORT 2
ADDRESS A8-A15
- 67 -
Publication Release Date: November 21, 2005
Revision A5