25AA040/25LC040/25C040
FIGURE 3-1:
CS
0
SCK
instruction
SI
0
0
0
0
A8
0
1
1
A7
6
lower address byte
5
4
3
2
1
A0
don鈥檛 care
data out
7
6
5
4
3
2
1
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
READ SEQUENCE
high impedance
SO
FIGURE 3-2:
CS
BYTE WRITE SEQUENCE
twc
0
SCK
instruction
SI
0
0
0
0
A8
0
1
0
A7
6
lower address byte
5
4
3
2
1
A0 7
6
5
data byte
4
3
2
1
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
high impedance
SO
FIGURE 3-3:
CS
0
SCK
1
PAGE WRITE SEQUENCE
2
3
4
5
6
7
8
9 10 11 13 14 15 16 17 18 19 20 21 22 23 24
instruction
SI
0
0
0
0 A8
0
1
0
A7 6
lower address byte
5
4
3
2
1
0
7
6
5
data byte 1
4
3
2
1
0
CS
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
SCK
data byte 2
SI
7
6
5
4
3
2
1
0
7
6
data byte 3
5
4
3
2
1
0
7
data byte n (16 max)
6
5
4
3
2
1
0
漏
1997 Microchip Technology Inc.
Preliminary
DS21204A-page 7