您的位置：维库电子市场网 > Datasheet > dsPIC30F4012

dsPIC30F4012 Datasheet

  • dsPIC30F4012

  • High-Performance, 16-bit Digital Signal Controllers

  • 2035.22KB

  • 238页

  • Microchip   Microchip

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

dsPIC30F2010
7.3.2
WRITING A BLOCK OF DATA
EEPROM
To write a block of data EEPROM, write to all sixteen
latches first, then set the NVMCON register and
program the block.
EXAMPLE 7-5:
MOV
MOV
MOV
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
MOV
DISI
MOV
MOV
MOV
MOV
BSET
NOP
NOP
DATA EEPROM BLOCK WRITE
#LOW_ADDR_WORD,W0
#HIGH_ADDR_WORD,W1
W1
,
TBLPAG
#data1,W2
W2
,
[
W0]++
#data2,W2
W2
,
[
W0]++
#data3,W2
W2
,
[
W0]++
#data4,W2
W2
,
[
W0]++
#data5,W2
W2
,
[
W0]++
#data6,W2
W2
,
[
W0]++
#data7,W2
W2
,
[
W0]++
#data8,W2
W2
,
[
W0]++
#data9,W2
W2
,
[
W0]++
#data10,W2
W2
,
[
W0]++
#data11,W2
W2
,
[
W0]++
#data12,W2
W2
,
[
W0]++
#data13,W2
W2
,
[
W0]++
#data14,W2
W2
,
[
W0]++
#data15,W2
W2
,
[
W0]++
#data16,W2
W2
,
[
W0]++
#0x400A,W0
W0
,
NVMCON
#5
#0x55,W0
W0
,
NVMKEY
#0xAA,W1
W1
,
NVMKEY
NVMCON,#WR
; Init pointer
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Get 1st data
write data
Get 2nd data
write data
Get 3rd data
write data
Get 4th data
write data
Get 5th data
write data
Get 6th data
write data
Get 7th data
write data
Get 8th data
write data
Get 9th data
write data
Get 10th data
write data
Get 11th data
write data
Get 12th data
write data
Get 13th data
write data
Get 14th data
write data
Get 15th data
write data
Get 16th data
write data. The NVMADR captures last table access address.
Select data EEPROM for multi word op
Operate Key to allow program operation
Block all interrupts with priority <7
for next 5 instructions
; Write the 0x55 key
; Write the 0xAA key
; Start write cycle
7.4
Write Verify
7.5
Protection Against Spurious Write
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared;
also, the Power-up Timer prevents EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch or software malfunction.
DS70118G-page 52
漏
2006 Microchip Technology Inc.

dsPIC30F4012相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2025 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：
技术客服：

0571-85317607

网站技术支持

13606545031

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！