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dsPIC30F4012 Datasheet

  • dsPIC30F4012

  • High-Performance, 16-bit Digital Signal Controllers

  • 2035.22KB

  • 238页

  • Microchip   Microchip

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dsPIC30F2010
12.4.2
PWM PERIOD
12.5
The PWM period is specified by writing to the PRx reg-
ister. The PWM period can be calculated using
Equation 12-1.
Output Compare Operation During
CPU Sleep Mode
EQUATION 12-1:
PWM PERIOD
PWM period = [(PRx) + 1] 鈥?4 鈥?T
OSC
鈥?/div>
(TMRx prescale value)
PWM frequency is defined as 1 / [PWM period].
When the selected TMRx is equal to its respective
period register, PRx, the following four events occur on
the next increment cycle:
鈥?TMRx is cleared.
鈥?The OCx pin is set.
- Exception 1: If PWM duty cycle is 0x0000,
the OCx pin will remain low.
- Exception 2: If duty cycle is greater than PRx,
the pin will remain high.
鈥?The PWM duty cycle is latched from OCxRS into
OCxR.
鈥?The corresponding timer interrupt flag is set.
See Figure 12-1 for key PWM period comparisons.
Timer3 is referred to in the figure for clarity.
When the CPU enters the Sleep mode, all internal
clocks are stopped. Therefore, when the CPU enters
the Sleep state, the output compare channel will drive
the pin to the active state that was observed prior to
entering the CPU Sleep state.
For example, if the pin was high when the CPU
entered the Sleep state, the pin will remain high. Like-
wise, if the pin was low when the CPU entered the
Sleep state, the pin will remain low. In either case, the
output compare module will resume operation when
the device wakes up.
12.6
Output Compare Operation During
CPU Idle Mode
When the CPU enters the Idle mode, the output
compare module can operate with full functionality.
The output compare channel will operate during the
CPU Idle mode if the OCSIDL bit (OCxCON<13>) is at
logic 鈥?鈥?and the selected time base (Timer2 or Timer3)
is enabled and the TSIDL bit of the selected timer is
set to logic 鈥?鈥?
FIGURE 12-1:
PWM OUTPUT TIMING
Period
Duty Cycle
TMR3 = PR3
T3IF =
1
(Interrupt Flag)
OCxR = OCxRS
TMR3 = PR3
T3IF =
1
(Interrupt Flag)
OCxR = OCxRS
TMR3 = Duty Cycle (OCxR)
TMR3 = Duty Cycle (OCxR)
12.7
Output Compare Interrupts
The output compare channels have the ability to gener-
ate an interrupt on a compare match, for whichever
Match mode has been selected.
For all modes except the PWM mode, when a compare
event occurs, the respective interrupt flag (OCxIF) is
asserted and an interrupt will be generated, if enabled.
The OCxIF bit is located in the corresponding IFS
status register, and must be cleared in software. The
interrupt is enabled via the respective compare inter-
rupt enable (OCxIE) bit, located in the corresponding
IEC Control register.
For the PWM mode, when an event occurs, the respec-
tive timer interrupt flag (T2IF or T3IF) is asserted and
an interrupt will be generated, if enabled. The IF bit is
located in the IFS0 status register, and must be cleared
in software. The interrupt is enabled via the respective
timer interrupt enable bit (T2IE or T3IE), located in the
IEC0 Control register. The output compare interrupt
flag is never set during the PWM mode of operation.
漏
2006 Microchip Technology Inc.
DS70118G-page 73

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