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dsPIC30F6010 Datasheet

  • dsPIC30F6010

  • High-Performance, 16-Bit Digital Signal Controllers

  • 2082.31KB

  • 222页

  • Microchip   Microchip

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dsPIC30F6010
2.3
Divide Support
The dsPIC devices feature a 16/16-bit signed fractional
divide operation, as well as 32/16-bit and 16/16-bit
signed and unsigned integer divide operations, in the
form of single instruction iterative divides. The following
instructions and data sizes are supported:
1.
2.
3.
4.
5.
DIVF
鈥?16/16 signed fractional divide
DIV.sd
鈥?32/16 signed divide
DIV.ud
鈥?32/16 unsigned divide
DIV.sw
鈥?16/16 signed divide
DIV.uw
鈥?16/16 unsigned divide
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g. a series
of discrete divide instructions) will not function correctly
because the instruction flow depends on RCOUNT. The
divide instruction does not automatically set up the
RCOUNT value, and it must, therefore, be explicitly and
correctly specified in the
REPEAT
instruction, as shown
in Table 2-1 (REPEAT will execute the target instruction
{operand value+1} times). The REPEAT loop count must
be set up for 18 iterations of the
DIV/DIVF
instruction.
Thus, a complete divide operation requires 19 cycles.
Note:
The Divide flow is interruptible. However,
the user needs to save the context as
appropriate.
TABLE 2-1:
DIVF
DIV.sd
DIVIDE INSTRUCTIONS
Instruction
Function
Signed fractional divide: Wm/Wn
鈫?/div>
W0; Rem
鈫?/div>
W1
Signed divide: (Wm+1:Wm)/Wn
鈫?/div>
W0; Rem
鈫?/div>
W1
Signed divide: Wm/Wn
鈫?/div>
W0; Rem
鈫?/div>
W1
Unsigned divide: (Wm+1:Wm)/Wn
鈫?/div>
W0; Rem
鈫?/div>
W1
Unsigned divide: Wm/Wn
鈫?/div>
W0; Rem
鈫?/div>
W1
A block diagram of the DSP engine is shown in
Figure 2-2.
DIV.sw (or DIV.s)
DIV.ud
DIV.uw (or DIV.u)
2.4
DSP Engine
The DSP engine consists of a high speed 17-bit x
17-bit multiplier, a barrel shifter, and a 40-bit adder/
Subtractor (with two target accumulators, round and
saturation logic).
The dsPIC30F devices have a single instruction flow
which can execute either DSP or MCU instructions.
Many of the hardware resources are shared between
the DSP and MCU instructions. For example, the
instruction set has both DSP and MCU Multiply
instructions which use the same hardware multiplier.
The DSP engine also has the capability to perform inher-
ent accumulator-to-accumulator operations, which
require no additional data. These instructions are
ADD,
SUB
and
NEG.
The DSP engine has various options selected through
various bits in the CPU Core Configuration Register
(CORCON), as listed below:
1.
2.
3.
4.
5.
6.
7.
Fractional or integer DSP multiply (IF).
Signed or unsigned DSP multiply (US).
Conventional or convergent rounding (RND).
Automatic saturation on/off for AccA (SATA).
Automatic saturation on/off for AccB (SATB).
Automatic saturation on/off for writes to data
memory (SATDW).
Accumulator Saturation mode selection
(ACCSAT).
Note:
For CORCON layout, see Table 4-2.
TABLE 2-2:
Instruction
CLR
ED
EDAC
MAC
MOVSAC
MPY
MPY.N
MSC
DSP INSTRUCTION
SUMMARY
Algebraic Operation
A=0
A = (x 鈥?y)
2
A = A + (x 鈥?y)
2
A = A + (x * y)
No change in A
A=x*y
A=鈥搙*y
A=A鈥搙*y
DS70119D-page 14
Preliminary
铮?/div>
2004 Microchip Technology Inc.

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