您的位置：维库电子市场网 > Datasheet > dsPIC30F6010

dsPIC30F6010 Datasheet

  • dsPIC30F6010

  • High-Performance, 16-Bit Digital Signal Controllers

  • 2082.31KB

  • 222页

  • Microchip   Microchip

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

dsPIC30F6010
5.4
Interrupt Sequence
5.5
Alternate Vector Table
All interrupt event flags are sampled in the beginning of
each instruction cycle by the IFSx registers. A pending
interrupt request (IRQ) is indicated by the flag bit being
equal to a 鈥?鈥?in an IFSx register. The IRQ will cause an
interrupt to occur if the corresponding bit in the interrupt
enable (IECx) register is set. For the remainder of the
instruction cycle, the priorities of all pending interrupt
requests are evaluated.
If there is a pending IRQ with a priority level greater
than the current processor priority level in the IPL bits,
the processor will be interrupted.
The processor then stacks the current program counter
and the low byte of the processor status register (SRL),
as shown in Figure 5-2. The low byte of the status reg-
ister contains the processor priority level at the time,
prior to the beginning of the interrupt cycle. The proces-
sor then loads the priority level for this interrupt into the
status register. This action will disable all lower priority
interrupts until the completion of the Interrupt Service
Routine.
In Program Memory, the Interrupt Vector Table (IVT) is
followed by the Alternate Interrupt Vector Table (AIVT),
as shown in Figure 5-1. Access to the Alternate Vector
Table is provided by the ALTIVT bit in the INTCON2
register. If the ALTIVT bit is set, all interrupt and excep-
tion processes will use the alternate vectors instead of
the default vectors. The alternate vectors are organized
in the same manner as the default vectors. The AIVT
supports emulation and debugging efforts by providing
a means to switch between an application and a sup-
port environment, without requiring the interrupt vec-
tors to be reprogrammed. This feature also enables
switching between applications for evaluation of
different software algorithms at run time.
If the AIVT is not required, the program memory allo-
cated to the AIVT may be used for other purposes.
AIVT is not a protected section and may be freely
programmed by the user.
5.6
Fast Context Saving
FIGURE 5-2:
0x0000 15
Stack Grows Towards
Higher Address
INTERRUPT STACK
FRAME
0
A context saving option is available using shadow reg-
isters. Shadow registers are provided for the DC, N,
OV, Z and C bits in SR, and the registers W0 through
W3. The shadows are only one level deep. The shadow
registers are accessible using the
PUSH.S
and
POP.S
instructions only.
When the processor vectors to an interrupt, the
PUSH.S
instruction can be used to store the current
value of the aforementioned registers into their
respective shadow registers.
If an ISR of a certain priority uses the
PUSH.S
and
POP.S
instructions for fast context saving, then a
higher priority ISR should not include the same instruc-
tions. Users must save the key registers in software
during a lower priority interrupt, if the higher priority ISR
uses fast context saving.
PC<15:0>
SRL IPL3 PC<22:16>
W15 (before
CALL)
W15 (after
CALL)
POP : [--W15]
PUSH : [W15++]
<Free Word>
Note 1:
The user can always lower the priority level
by writing a new value into SR. The Interrupt
Service Routine must clear the interrupt flag
bits in the IFSx register before lowering the
processor interrupt priority, in order to avoid
recursive interrupts.
2:
The IPL3 bit (CORCON<3>) is always clear
when interrupts are being processed. It is
set only during execution of traps.
5.7
External Interrupt Requests
The interrupt controller supports five external interrupt
request signals, INT0-INT4. These inputs are edge
sensitive; they require a low-to-high or a high-to-low
transition to generate an interrupt request. The
INTCON2 register has five bits, INT0EP-INT4EP, that
select the polarity of the edge detection circuitry.
The
RETFIE
(Return from Interrupt) instruction will
unstack the program counter and status registers to
return the processor to its state prior to the interrupt
sequence.
5.8
Wake-up from Sleep and Idle
The interrupt controller may be used to wake up the
processor from either Sleep or Idle modes, if Sleep or
Idle mode is active when the interrupt is generated.
If an enabled interrupt request of sufficient priority is
received by the interrupt controller, then the standard
interrupt request is presented to the processor. At the
same time, the processor will wake-up from Sleep or
Idle and begin execution of the Interrupt Service
Routine (ISR) needed to process the interrupt request.
铮?/div>
2004 Microchip Technology Inc.
Preliminary
DS70119D-page 41

dsPIC30F6010相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2024 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：

0571-85317607

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！