dsPIC30F6010
8.3
Input Change Notification Module
The Input Change Notification module provides the
dsPIC30F devices the ability to generate interrupt
requests to the processor in response to a change-of-
state on selected input pins. This module is capable of
detecting input change-of-states even in Sleep mode,
when the clocks are disabled. There are 22 external
signals (CN0 through CN21) that may be selected
(enabled) for generating an interrupt request on a
change-of-state.
Please refer to the Pin Diagram on page 3 for CN pin
locations.
TABLE 8-2:
SFR
Name
CNEN1
CNEN2
CNPU1
CNPU2
Legend:
Addr.
00C0
00C2
00C4
00C6
INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 15-8)
Bit 15
CN15IE
鈥?/div>
Bit 14
CN14IE
鈥?/div>
Bit 13
CN13IE
鈥?/div>
Bit 12
CN12IE
鈥?/div>
Bit 11
CN11IE
鈥?/div>
Bit 10
CN10IE
鈥?/div>
Bit 9
CN9IE
鈥?/div>
CN9PUE
鈥?/div>
Bit 8
CN8IE
鈥?/div>
CN8PUE
鈥?/div>
Reset State
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
u
= uninitialized bit
TABLE 8-3:
SFR
Name
CNEN1
CNEN2
CNPU1
CNPU2
Legend:
Addr.
00C0
00C2
00C4
00C6
INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 7-0)
Bit 7
CN7IE
鈥?/div>
CN7PUE
鈥?/div>
Bit 6
CN6IE
鈥?/div>
CN6PUE
鈥?/div>
Bit 5
CN5IE
CN21IE
CN5PUE
Bit 4
CN4IE
CN20IE
CN4PUE
Bit 3
CN3IE
CN19IE
CN3PUE
Bit 2
CN2IE
CN18IE
CN2PUE
Bit 1
CN1IE
CN17IE
CN1PUE
Bit 0
CN0IE
CN16IE
CN0PUE
CN16PUE
Reset State
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE
u
= uninitialized bit
DS70119D-page 56
Preliminary
铮?/div>
2004 Microchip Technology Inc.
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