鈥?/div>
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
A/D Result Register
ADCS1
ADCS0
Legend:
x
= unknown,
u
= unchanged,
q
= value depends on condition, - = unimplemented read as '0', r = reserved.
Shaded locations are unimplemented, read as 鈥?鈥?
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC12CE67X, always maintain these bits clear.
漏
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 13