PIC12CE674 Datasheet

  • PIC12CE674

  • 8-Pin, 8-Bit CMOS Microcontroller with A/D Converter and EEP...

  • 1264.35KB

  • 129页

  • Microchip   Microchip

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PIC12CE67X
TABLE 4-1:
Address Name
PIC12CE67X SPECIAL FUNCTION REGISTER SUMMARY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on
all other
Resets
(3)
Bank 0
00h
(1)
01h
02h
(1)
03h
(1)
04h
(1)
05h
06h
07h
08h
09h
0Ah
(1,2)
0Bh
(1)
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
INDF
TMR0
PCL
STATUS
FSR
GPIO
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
PCLATH
INTCON
PIR1
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
ADRES
ADCON0
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module鈥檚 register
Program Counter's (PC) Least Signi铿乧ant Byte
IRP
(4)
RP1
(4)
RP0
TO
PD
Z
DC
C
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
GP4
GP3
GP2
GP1
GP0
11xx xxxx
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
PEIE
ADIF
鈥?/div>
T0IE
鈥?/div>
Write Buffer for the upper 5 bits of the Program Counter
INTE
鈥?/div>
GPIE
鈥?/div>
T0IF
鈥?/div>
INTF
鈥?/div>
GPIF
鈥?/div>
---0 0000
0000 000x
-0-- ----
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
xxxx xxxx
r
CHS1
CHS0
GO/DONE
r
ADON
0000 0000
0000 0000
uuuu uuuu
0000 0000
000q quuu
uuuu uuuu
11uu uuuu
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
---0 0000
0000 000u
-0-- ----
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
uuuu uuuu
0000 0000
Indirect data memory address pointer
SCL
SDA
GP5
Unimplemented
Unimplemented
Unimplemented
Unimplemented
鈥?/div>
GIE
鈥?/div>
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
A/D Result Register
ADCS1
ADCS0
Legend:
x
= unknown,
u
= unchanged,
q
= value depends on condition, - = unimplemented read as '0', r = reserved.
Shaded locations are unimplemented, read as 鈥?鈥?
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC12CE67X, always maintain these bits clear.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 13

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