PIC12CE674 Datasheet

IC型号：
PIC12CE674
PDF描述：
8-Pin, 8-Bit CMOS Microcontroller with A/D Converter and EEP...
文件大小：
1264.35KB
PDF页数：
129页
芯片厂家：
Microchip

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PIC12CE67X

8.1

A/D Sampling Requirements

For the A/D converter to meet its speci铿乪d accuracy,

the charge holding capacitor (C

HOLD

) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 8-4. The source

impedance (R

) and the internal sampling switch (R

)

impedance directly affect the time required to charge

the capacitor C

HOLD

. The sampling switch (R

)

impedance varies over the device voltage (V

), see

Figure 8-4.

The maximum recommended imped-

ance for analog sources is 10 k鈩?

After the analog

input channel is selected (changed) this acquisition

must be done before the conversion can be started.

To calculate the minimum acquisition time, Equation 8-

1 may be used. This equation assumes that 1/2 LSb

error is used (512 steps for the A/D). The 1/2 LSb error

is the maximum error allowed for the A/D to meet its

speci铿乪d resolution.

Note 1:

The reference voltage (V

REF

) has no

effect on the equation, since it cancels

itself out.

Note 2:

The charge holding capacitor (C

HOLD

) is

not discharged after each conversion.

Note 3:

The maximum recommended impedance

for analog sources is 10 k鈩? This is

required to meet the pin leakage speci铿?

cation.

Note 4:

After a conversion has completed, a

2.0 T

delay must complete before

acquisition can begin again. During this

time the holding capacitor is not con-

nected to the selected A/D input channel.

EXAMPLE 8-1:

CALCULATING THE

MINIMUM REQUIRED

SAMPLE TIME

EQUATION 8-1:

A/D MINIMUM CHARGING

TIME

ACQ

= Ampli铿乪r Settling Time +

Holding Capacitor Charging Time +

Temperature Coef铿乧ient

ACQ

= 5

碌s

+ Tc + [(Temp - 25掳C)(0.05

碌s/掳C)]

-C

HOLD

+ R

) ln(1/512)

-51.2 pF (1 k鈩?+ 7 k鈩?+ 10 k鈩? ln(0.0020)

-51.2 pF (18 k鈩? ln(0.0020)

-0.921

碌s

(-6.2146)

5.724

碌s

ACQ

= 5

碌s

+ 5.724

碌s

+ [(50掳C - 25掳C)(0.05

碌s/掳C)]

10.724

碌s

+ 1.25

碌s

11.974

碌s

HOLD

= (V

REF

- (V

REF

/512)) 鈥?(1 - e

(-Tc/C

HOLD

+ R

))

)

Tc = -(51.2 pF)(1 k鈩?+ R

+ R

) ln(1/511)

Example 8-1 shows the calculation of the minimum

required acquisition time T

ACQ

. This calculation is

based on the following system assumptions.

Rs = 10 k

鈩?/div>

1/2 LSb error

= 5V

鈫?/div>

Rss = 7 k

鈩?/div>

Temp (system max.) = 50

掳

HOLD

= 0 @ t = 0

FIGURE 8-4:

ANALOG INPUT MODEL

= 0.6V

鈮?/div>

Sampling

Switch

SS R

HOLD

= DAC capacitance

= 51.2 pF

Legend C

= input capacitance

= threshold voltage

I leakage = leakage current at the pin due to

various junctions

HOLD

= interconnect resistance

= sampling switch

= sample/hold capacitance (from DAC)

RAx

5 pF

= 0.6V

I leakage

卤

500 nA

5 6 7 8 9 10 11

Sampling Switch

( k鈩?)

DS40181B-page 40

Preliminary

漏

1998 Microchip Technology Inc.

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