您的位置：维库电子市场网 > Datasheet > PIC12CE674

PIC12CE674 Datasheet

  • PIC12CE674

  • 8-Pin, 8-Bit CMOS Microcontroller with A/D Converter and EEP...

  • 1264.35KB

  • 129页

  • Microchip   Microchip

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

PIC12CE67X
9.5
Interrupts
There are four sources of interrupt:
Interrupt Sources
TMR0 over铿俹w interrupt
External interrupt GP2/INT pin
GPIO Port change interrupts (pins GP0, GP1, GP3)
A/D Interrupt
The interrupt control register (INTCON) records individ-
ual interrupt requests in 铿俛g bits. It also has individual
and global interrupt enable bits.
Note:
Individual interrupt 铿俛g bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
The 鈥渞eturn from interrupt鈥?instruction,
RETFIE,
exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
The GP2/INT, GPIO port change interrupt and the
TMR0 over铿俹w interrupt 铿俛gs are contained in the
INTCON register.
The peripheral interrupt 铿俛g ADIF, is contained in the
special function register PIR1. The corresponding
interrupt enable bit is contained in special function reg-
ister PIE1, and the peripheral interrupt enable bit is
contained in special function register INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt 铿俛g bits. The interrupt 铿俛g bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as GPIO change
interrupt, the interrupt latency will be three or four
instruction cycles. The exact latency depends when the
interrupt event occurs (Figure 8-15). The latency is the
same for one or two cycle instructions. Individual inter-
rupt 铿俛g bits are set regardless of the status of their
corresponding mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt鈥檚 铿俛g bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
FIGURE 9-14: INTERRUPT LOGIC
T0IF
T0IE
INTF
INTE
GPIF
GPIE
ADIF
ADIE
PEIE
Interrupt to CPU
Wakeup
(If in SLEEP mode)
GIE
DS40181B-page 54
Preliminary
漏
1998 Microchip Technology Inc.

PIC12CE674相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2024 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：

0571-85317607

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！