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PIC12CE674 Datasheet

  • PIC12CE674

  • 8-Pin, 8-Bit CMOS Microcontroller with A/D Converter and EEP...

  • 1264.35KB

  • 129页

  • Microchip   Microchip

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PIC12CE67X
9.7
Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscil-
lator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKIN pin. That means that the WDT will
run, even if the clock on the OSC1/CLKIN and OSC2/
CLKOUT pins of the device has been stopped, for
example, by execution of a
SLEEP
instruction. During
normal operation, a WDT time-out generates a device
RESET (Watchdog Timer Reset). If the device is in
SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The WDT can be permanently
disabled by clearing con铿乬uration bit WDTE
(Section 9.1).
9.7.1
WDT PERIOD
The
CLRWDT
and
SLEEP
instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out early and generating a premature
device RESET condition.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
9.7.2
WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under worst
case conditions (V
DD
= Min., Temperature = Max., and
max. WDT prescaler) it may take several seconds
before a WDT time-out occurs.
Note:
When the prescaler is assigned to the
WDT, always execute a
CLRWDT
instruction
before changing the prescale value, other-
wise a WDT reset may occur.
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with tempera-
ture, V
DD
and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
FIGURE 9-16: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 7-5)
0
WDT Timer
1
M
U
X
Postscaler
8
8 - to - 1 MUX
WDT
Enable Bit
PSA
To TMR0 (Figure 7-5)
0
MUX
1
PSA
PS2:PS0
Note: PSA and PS2:PS0 are bits in the OPTION register.
WDT
Time-out
FIGURE 9-17: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
2007h
81h
Name
Con铿乬. bits
(1)
OPTION
Bit 7
MCLRE
GPPU
Bit 6
CP1
INTEDG
Bit 5
CP0
T0CS
Bit 4
PWRTE
T0SE
Bit 3
WDTE
PSA
Bit 2
FOSC2
PS2
Bit 1
FOSC1
PS1
Bit 0
FOSC0
PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 9-1 for operation of these bits. Not all CP0 and CP1 bits are shown.
漏
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 57

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