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PD
TO, PD
00
0000
0110
0011
The power-down status bit, PD is
cleared. Time-out status bit, TO is
set. Watchdog Timer and its pres-
caler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
RLF
f,d
SLEEP
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example
1
1
RLF
REG1,0
REG1
C
=
=
=
=
=
1110 0110
0
1110 0110
1100 1100
1
Words:
Cycles:
Example:
1
1
SLEEP
Before Instruction
After Instruction
REG1
W
C
漏
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 71