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PIC17C752 Datasheet

  • PIC17C752

  • High-Performance 8-bit CMOS EPROM Microcontrollers with 10-b...

  • 3053.02KB

  • 304页

  • Microchip   Microchip

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PIC17C75X
6.1
Interrupt Status Register (INTSTA)
The Interrupt Status/Control register (INTSTA) records
the individual interrupt requests in 铿俛g bits, and con-
tains the individual interrupt enable bits (not for the
peripherals).
The PEIF bit is a read only, bit wise OR of all the periph-
eral 铿俛g bits in the PIR registers (Figure 6-5 and
Figure 6-6).
T0IF, INTF, T0CKIF, and PEIF get set by
their speci铿乪d condition, even if the corre-
sponding interrupt enable bit is clear (inter-
rupt disabled) or the GLINTD bit is set (all
interrupts disabled).
Care should be taken when clearing any of the INTSTA
register enable bits when interrupts are enabled
(GLINTD is clear). If any of the INTSTA 铿俛g bits (T0IF,
INTF, T0CKIF, or PEIF) are set in the same instruction
cycle as the corresponding interrupt enable bit is
cleared, the device will vector to the reset address
(0x00).
When disabling any of the INTSTA enable bits, the
GLINTD bit should be set (disabled).
Note:
FIGURE 6-2:
R-0
PEIF
bit7
bit 7:
INTSTA REGISTER (ADDRESS: 07h, UNBANKED)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
T0CKIF T0IF
INTF
PEIE T0CKIE
T0IE
INTE
bit0
PEIF:
Peripheral Interrupt Flag bit
This bit is the OR of all peripheral interrupt 铿俛g bits AND鈥檈d with their corresponding enable bits.
1 = A peripheral interrupt is pending
0 = No peripheral interrupt is pending
R = Readable bit
W = Writable bit
- n = Value at POR reset
bit 6:
T0CKIF:
External Interrupt on T0CKI Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to vector (18h).
1 = The software speci铿乪d edge occurred on the RA1/T0CKI pin
0 = The software speci铿乪d edge did not occur on the RA1/T0CKI pin
T0IF:
TMR0 Over铿俹w Interrupt Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to vector (10h).
1 = TMR0 over铿俹wed
0 = TMR0 did not over铿俹w
INTF:
External Interrupt on INT Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to vector (08h).
1 = The software speci铿乪d edge occurred on the RA0/INT pin
0 = The software speci铿乪d edge did not occur on the RA0/INT pin
PEIE:
Peripheral Interrupt Enable bit
This bit enables all peripheral interrupts that have their corresponding enable bits set.
1 = Enable peripheral interrupts
0 = Disable peripheral interrupts
T0CKIE:
External Interrupt on T0CKI Pin Enable bit
1 = Enable software speci铿乪d edge interrupt on the RA1/T0CKI pin
0 = Disable interrupt on the RA1/T0CKI pin
T0IE:
TMR0 Over铿俹w Interrupt Enable bit
1 = Enable TMR0 over铿俹w interrupt
0 = Disable TMR0 over铿俹w interrupt
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
INTE:
External Interrupt on RA0/INT Pin Enable bit
1 = Enable software speci铿乪d edge interrupt on the RA0/INT pin
0 = Disable software speci铿乪d edge interrupt on the RA0/INT pin
DS30264A-page 30
Preliminary
漏
1997 Microchip Technology Inc.

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