PIC17C752 Datasheet

IC型号：
PIC17C752
PDF描述：
High-Performance 8-bit CMOS EPROM Microcontrollers with 10-b...
文件大小：
3053.02KB
PDF页数：
304页
芯片厂家：
Microchip

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PIC17C75X

TABLE 7-3:

Address

Name

SPECIAL FUNCTION REGISTERS

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

resets (3)

Unbanked

00h

01h

02h

03h

(1)

04h

05h

06h

(2)

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

Bank 0

10h

11h

12h

13h

14h

15h

16h

17h

Bank 1

10h

11h

12h

13h

14h

15h

16h

17h

Legend:

Note 1:

DDRC

PORTC

DDRD

PORTD

DDRE

PORTE

PIR1

PIE1

Data direction register for PORTC

RC7/

AD7

RC6/

AD6

RC5/

AD5

RC4/

AD4

RC3/

AD3

RC2/

AD2

RC1/

AD1

RC0/

AD0

1111 1111 1111 1111

xxxx xxxx uuuu uuuu

1111 1111 1111 1111

RD4/

AD12

RD3/

AD11

RD2/

AD10

RD1/

AD9

RD0/

AD8

xxxx xxxx uuuu uuuu

---- 1111 ---- 1111

鈥?/div>

TMR1IF

TMR1IE

RE3/

CAP4

CA2IF

CA2IE

RE2/WR

CA1IF

CA1IE

RE1/OE

TX1IF

TX1IE

RE0/ALE

---- xxxx ---- uuuu

RC1IF

RC1IE

x000 0010 u000 0010

0000 0000 0000 0000

PORTA

DDRB

PORTB

RCSTA1

RCREG1

TXSTA1

TXREG1

SPBRG1

RBPU

鈥?/div>

RA5/TX1/

CK1

RA4/RX1/ RA3/SDI/

DT1

SDA

RA2/SS/

SCL

RA1/T0CKI

RA0/INT

0-xx xxxx 0-uu uuuu

1111 1111 1111 1111

RB4/

TCLK12

CREN

RB3/

PWM2

鈥?/div>

RB2/

PWM1

FERR

RB1/

CAP2

OERR

RB0/

CAP1

RX9D

xxxx xxxx uuuu uuuu

0000 -00x 0000 -00u

xxxx xxxx uuuu uuuu

SYNC

鈥?/div>

TRMT

TX9D

0000 --1x 0000 --1u

xxxx xxxx uuuu uuuu

INDF0

FSR0

PCL

PCLATH

ALUSTA

T0STA

CPUSTA

INTSTA

INDF1

FSR1

WREG

TMR0L

TMR0H

TBLPTRL

TBLPTRH

BSR

Uses contents of FSR0 to address data memory (not a physical register)

Indirect data memory address pointer 0

Low order 8-bits of PC

Holding register for upper 8-bits of PC

FS3

INTEDG

鈥?/div>

PEIF

FS2

T0SE

鈥?/div>

T0CKIF

FS1

T0CS

STKAV

T0IF

FS0

T0PS3

GLINTD

INTF

T0PS2

PEIE

T0PS1

T0CKIE

T0PS0

POR

T0IE

鈥?/div>

BOR

INTE

---- ---- ---- ----

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

1111 xxxx 1111 uuuu

0000 000- 0000 000-

--11 1100 --11 qquu

0000 0000 0000 0000

---- ---- ---- ----

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

Uses contents of FSR1 to address data memory (not a physical register)

Indirect data memory address pointer 1

Working register

TMR0 register; low byte

TMR0 register; high byte

Low byte of program memory table pointer

High byte of program memory table pointer

Bank select register

Data direction register for PORTB

RB7/

SDO

SPEN

RB6/

SCK

RX9

RB5/

TCLK3

SREN

Serial port receive register

CSRC

TX9

TXEN

Serial Port Transmit Register (for USART1)

Baud Rate Generator Register (for USART1)

Data direction register for PORTD

RD7/

AD15

RD6/

AD14

RD5/

AD13

Data direction register for PORTE

鈥?/div>

RBIF

RBIE

鈥?/div>

TMR3IF

TMR3IE

鈥?/div>

TMR2IF

TMR2IE

x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. Shaded cells are unimplemented, read as '0'.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose contents are updated

from or transferred to the upper byte of the program counter.

The TO and PD status bits in CPUSTA are not affected by a MCLR reset.

Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.

DS30264A-page 44

Preliminary

漏

1997 Microchip Technology Inc.

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