PIC17C752 Datasheet

IC型号：
PIC17C752
PDF描述：
High-Performance 8-bit CMOS EPROM Microcontrollers with 10-b...
文件大小：
3053.02KB
PDF页数：
304页
芯片厂家：
Microchip

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PIC17C75X

TABLE 7-3:

Address

Bank 2

10h

11h

12h

13h

14h

15h

16h

17h

Bank 3

10h

11h

12h

13h

14h

15h

16h

17h

Bank 4:

10h

11h

12h

13h

14h

15h

16h

17h

Bank 5:

10h

11h

12h

13h

14h

15h

16h

17h

Legend:

Note 1:

DDRF

PORTF

DDRG

PORTG

ADCON0

ADCON1

ADRESL

ADRESH

Data Direction Register for PORTF

RF7/

AN11

RF6/

AN10

RF5/

AN9

RF4/

AN8

RF3/

AN7

RF2/

AN6

RF1/

AN5

RF0/

AN4

1111 1111 1111 1111

0000 0000 0000 0000

1111 1111 1111 1111

RG4/

CAP3

CHS0

鈥?/div>

RG3/

AN0

鈥?/div>

PCFG3

RG2/

AN1

GO/DONE

PCFG2

RG1/

AN2

鈥?/div>

PCFG1

RG0/

AN3

ADON

PCFG0

xxxx 0000 uuuu 0000

0000 -0-0 0000 -0-0

000- 0000 000- 0000

xxxx xxxx uuuu uuuu

PIR2

PIE2

Unimplemented

RCSTA2

RCREG2

TXSTA2

TXREG2

SPBRG2

SSPIF

SSPIE

鈥?/div>

SPEN

BCLIF

BCLIE

鈥?/div>

RX9

ADIF

ADIE

鈥?/div>

SREN

鈥?/div>

CREN

CA4IF

CA4IE

鈥?/div>

CA3IF

CA3IE

鈥?/div>

FERR

TX2IF

TX2IE

鈥?/div>

OERR

RC2IF

RC2IE

鈥?/div>

RX9D

000- 0010 000- 0010

000- 0000 000- 0000

---- ---- ---- ----

0000 -00x 0000 -00u

xxxx xxxx uuuu uuuu

鈥?/div>

TRMT

TX9D

0000 --1x 0000 --1u

xxxx xxxx uuuu uuuu

PW1DCL

PW2DCL

PW1DCH

PW2DCH

CA2L

CA2H

TCON1

TCON2

DC1

DC9

DC0

DC8

鈥?/div>

TM2PW2

DC7

鈥?/div>

DC6

鈥?/div>

DC5

鈥?/div>

DC4

鈥?/div>

DC3

鈥?/div>

DC2

xx-- ---- uu-- ----

xx0- ---- uu0- ----

xxxx xxxx uuuu uuuu

CA1ED1

CA1ED0

T16

TMR3CS

TMR3ON

TMR2CS

TMR2ON

TMR1CS

0000 0000 0000 0000

TMR1ON

0000 0000 0000 0000

TMR1

TMR2

TMR3L

TMR3H

PR1

PR2

PR3L/CA1L

PR3H/CA1H

Timer1鈥檚 register

Timer2鈥檚 register

Timer3鈥檚 register; low byte

Timer3鈥檚 register; high byte

Timer1鈥檚 period register

Timer2鈥檚 period register

Timer3鈥檚 period register - low byte/capture1 register; low byte

Timer3鈥檚 period register - high byte/capture1 register; high byte

xxxx xxxx uuuu uuuu

Name

SPECIAL FUNCTION REGISTERS (Cont.鈥檇)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

resets (3)

Capture2 low byte

Capture2 high byte

CA2ED1 CA2ED0

CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3

Serial Port Receive Register for USART2

CSRC

TX9

TXEN

SYNC

Serial Port Transmit Register for USART2

Baud Rate Generator for USART2

Data Direction Register for PORTG

RG7/

RG6/

TX2/CK2 RX2/DT2

CHS3

ADCS1

CHS2

ADCS0

RG5/

PWM3

CHS1

ADFM

A/D Result Register low byte

A/D Result Register high byte

x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. Shaded cells are unimplemented, read as '0'.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose contents are updated

from or transferred to the upper byte of the program counter.

The TO and PD status bits in CPUSTA are not affected by a MCLR reset.

Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.

漏

1997 Microchip Technology Inc.

Preliminary

DS30264A-page 45

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