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PIC17C752 Datasheet

  • PIC17C752

  • High-Performance 8-bit CMOS EPROM Microcontrollers with 10-b...

  • 3053.02KB

  • 304页

  • Microchip   Microchip

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PIC17C75X
7.4.1
INDIRECT ADDRESSING REGISTERS
The PIC17C75X has four registers for indirect
addressing. These registers are:
鈥?INDF0 and FSR0
鈥?INDF1 and FSR1
Registers INDF0 and INDF1 are not physically imple-
mented. Reading or writing to these registers activates
indirect addressing, with the value in the correspond-
ing FSR register being the address of the data. The
FSR is an 8-bit register and allows addressing any-
where in the 256-byte data memory address range.
For banked memory, the bank of memory accessed is
speci铿乪d by the value in the BSR.
If 铿乴e INDF0 (or INDF1) itself is read indirectly via an
FSR, all '0's are read (Zero bit is set). Similarly, if
INDF0 (or INDF1) is written to indirectly, the operation
will be equivalent to a NOP, and the status bits are not
affected.
7.4.2
INDIRECT ADDRESSING OPERATION
A simple program to clear RAM from 20h - FFh is
shown in Example 7-1.
EXAMPLE 7-1:
MOVLW
MOVWF
BCF
BSF
BCF
MOVLW
CLRF
CPFSEQ
GOTO
:
:
INDIRECT ADDRESSING
;
;
;
;
;
;
;
;
;
;
;
LP
0x20
FSR0
ALUSTA,
ALUSTA,
ALUSTA,
END_RAM
INDF0
FSR0
LP
FS1
FS0
C
+ 1
FSR0 = 20h
Increment FSR
after access
C = 0
Addr(FSR) = 0
FSR0 = END_RAM+1?
NO, clear next
YES, All RAM is
cleared
7.5
Table Pointer (TBLPTRL and
TBLPTRH)
The indirect addressing capability has been enhanced
over that of the PIC16CXX family. There are two con-
trol bits associated with each FSR register. These two
bits con铿乬ure the FSR register to:
鈥?Auto-decrement the value (address) in the FSR
after an indirect access
鈥?Auto-increment the value (address) in the FSR
after an indirect access
鈥?No change to the value (address) in the FSR after
an indirect access
These control bits are located in the ALUSTA register.
The FSR1 register is controlled by the FS3:FS2 bits
and FSR0 is controlled by the FS1:FS0 bits.
When using the auto-increment or auto-decrement
features, the effect on the FSR is not re铿俥cted in the
ALUSTA register. For example, if the indirect address
causes the FSR to equal '0', the Z bit will not be set.
If the FSR register contains a value of 0h, an indirect
read will read 0h (Zero bit is set) while an indirect write
will be equivalent to a NOP (status bits are not
affected).
Indirect addressing allows single cycle data transfers
within the entire data space. This is possible with the
use of the
MOVPF
and
MOVFP
instructions, where
either 'p' or 'f' is speci铿乪d as INDF0 (or INDF1).
If the source or destination of the indirect address is in
banked memory, the location accessed will be deter-
mined by the value in the BSR.
File registers TBLPTRL and TBLPTRH form a 16-bit
pointer to address the 64K program memory space.
The table pointer is used by instructions
TABLWT
and
TABLRD.
The
TABLRD
and the
TABLWT
instructions allow trans-
fer of data between program and data space. The table
pointer serves as the 16-bit address of the data word
within the program memory. For a more complete
description of these registers and the operation of
Table Reads and Table Writes, see Section 8.0.
7.6
Table Latch (TBLATH, TBLATL)
The table latch (TBLAT) is a 16-bit register, with
TBLATH and TBLATL referring to the high and low
bytes of the register. It is not mapped into data or pro-
gram memory. The table latch is used as a temporary
holding latch during data transfer between program
and data memory (see
TABLRD, TABLWT, TLRD
and
TLWT
instruction descriptions). For a more complete
description of these registers and the operation of
Table Reads and Table Writes, see Section 8.0.
漏
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 51

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