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PIC17C752 Datasheet

  • PIC17C752

  • High-Performance 8-bit CMOS EPROM Microcontrollers with 10-b...

  • 3053.02KB

  • 304页

  • Microchip   Microchip

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PIC17C75X
12.1
Timer0 Operation
12.2
Using Timer0 with External Clock
When the T0CS (T0STA<5>) bit is set, TMR0 incre-
ments on the internal clock. When T0CS is clear, TMR0
increments on the external clock (RA1/T0CKI pin). The
external clock edge can be selected in software. When
the T0SE (T0STA<6>) bit is set, the timer will increment
on the rising edge of the RA1/T0CKI pin. When T0SE
is clear, the timer will increment on the falling edge of
the RA1/T0CKI pin. The prescaler can be programmed
to introduce a prescale of 1:1 to 1:256. The timer incre-
ments from 0000h to FFFFh and rolls over to 0000h.
On over铿俹w, the TMR0 Interrupt Flag bit (T0IF) is set.
The TMR0 interrupt can be masked by clearing the cor-
responding TMR0 Interrupt Enable bit (T0IE). The
TMR0 Interrupt Flag bit (T0IF) is automatically cleared
when vectoring to the TMR0 interrupt vector.
When an external clock input is used for Timer0, it is
synchronized with the internal phase clocks.
Figure 12-3 shows the synchronization of the external
clock. This synchronization is done after the prescaler.
The output of the prescaler (PSOUT) is sampled twice
in every instruction cycle to detect a rising or a falling
edge. The timing requirements for the external clock
are detailed in the electrical speci铿乧ation section.
12.2.1
DELAY FROM EXTERNAL CLOCK EDGE
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time TMR0 is actually
incremented. Figure 12-3 shows that this delay is
between 3T
OSC
and 7T
OSC
. Thus, for example, mea-
suring the interval between two edges (e.g. period) will
be accurate within
卤4T
OSC
(卤121 ns @ 33 MHz).
FIGURE 12-2: TIMER0 MODULE BLOCK DIAGRAM
Interrupt on over铿俹w
sets T0IF
(INTSTA<5>)
0
RA1/T0CKI
T0SE
(T0STA<6>)
T0CS
(T0STA<5>)
Fosc/4
1
Prescaler
(8 stage
async ripple
counter)
4
T0PS3:T0PS0
(T0STA<4:1>)
Q2
Q4
Synchronization
PSOUT
TMR0H<8> TMR0L<8>
FIGURE 12-3: TMR0 TIMING WITH EXTERNAL CLOCK (INCREMENT ON FALLING EDGE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Prescaler
output
(PSOUT)
Sampled
Prescaler
output
(note 1)
Increment
TMR0
(note 3)
(note 2)
TMR0
T0
T0 + 1
T0 + 2
Note 1: The delay from the T0CKI edge to the TMR0 increment is 3Tosc to 7Tosc.
2:
鈫?/div>
= PSOUT is sampled here.
3: The PSOUT high time is too short and is missed by the sampling circuit.
DS30264A-page 88
Preliminary
漏
1997 Microchip Technology Inc.

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