PIC18F6720 Datasheet

  • PIC18F6720

  • 64/80-Pin High-Performance,256 Kbit to 1 Mbit Enhanced Flash...

  • 3274.08KB

  • 380页

  • Microchip   Microchip

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PIC18F6520/8520/6620/8620/6720/8720
2.4
External Clock Input
FIGURE 2-5:
The EC and ECIO Oscillator modes require an external
clock source to be connected to the OSC1 pin. The
feedback device between OSC1 and OSC2 is turned
off in these modes to save current. There is a maximum
1.5
碌s
start-up required after a Power-on Reset, or
wake-up from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-4 shows the pin connections for the EC
Oscillator mode.
EXTERNAL CLOCK INPUT
OPERATION
(ECIO CONFIGURATION)
OSC1
Clock from
Ext. System
RA6
PIC18FXX20
I/O (OSC2)
2.5
HS/PLL
FIGURE 2-4:
EXTERNAL CLOCK INPUT
OPERATION
(EC CONFIGURATION)
OSC1
A Phase Locked Loop circuit (PLL) is provided as a
programmable option for users that want to multiply the
frequency of the incoming crystal oscillator signal by 4.
For an input clock frequency of 10 MHz, the internal
clock frequency will be multiplied to 40 MHz. This is
useful for customers who are concerned with EMI due
to high-frequency crystals.
The PLL is one of the modes of the FOSC<2:0> config-
uration bits. The oscillator mode is specified during
device programming.
The PLL can only be enabled when the oscillator con-
figuration bits are programmed for HS mode. If they are
programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1. Also, PLL operation cannot be changed 鈥渙n-
the-fly鈥? To enable or disable it, the controller must
either cycle through a Power-on Reset, or switch the
clock source from the main oscillator to the Timer1
oscillator and back again. See
Section 2.6 鈥淥scillator
Switching Feature鈥?/span>
for details on oscillator switching.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out that is called T
PLL
.
Clock from
Ext. System
F
OSC
/4
PIC18FXX20
OSC2
The ECIO Oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO Oscillator mode.
FIGURE 2-6:
PLL BLOCK DIAGRAM
HS Osc
PLL Enable
Phase
Comparator
F
IN
F
OUT
Loop
Filter
VCO
SYSCLK
(from Configuration
bit Register)
OSC2
Crystal
Osc
OSC1
Divide by 4
铮?/div>
2004 Microchip Technology Inc.
DS39609B-page 23
MUX

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