鈥?/div>
R/W-1
RI
R/W-1
TO
R/W-1
PD
R/W-1
POR
R/W-1
BOR
bit 0
TABLE 3-2:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Program
Counter
0000h
0000h
0000h
0000h
0000h
0000h
0000h
PC + 2
0000h
PC + 2
(1)
Condition
Power-on Reset
MCLR Reset during normal
operation
Software Reset during normal
operation
Stack Full Reset during normal
operation
Stack Underflow Reset during
normal operation
MCLR Reset during Sleep
WDT Reset
WDT Wake-up
Brown-out Reset
Interrupt wake-up from Sleep
RCON
Register
0--1 1100
0--u uuuu
0--0 uuuu
0--u uu11
0--u uu11
0--u 10uu
0--u 01uu
u--u 00uu
0--1 11u0
u--u 00uu
RI
1
u
0
u
u
u
1
u
1
u
TO
1
u
u
u
u
1
0
0
1
1
PD
1
u
u
u
u
0
1
0
1
0
POR
0
u
u
u
u
u
u
u
1
u
BOR
0
u
u
u
u
u
u
u
0
u
STKFUL
u
u
u
u
1
u
u
u
u
u
STKUNF
u
u
u
1
u
u
u
u
u
u
Legend:
u
= unchanged,
x
= unknown, 鈥?= unimplemented bit, read as 鈥?鈥?/div>
Note 1:
When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
铮?/div>
2004 Microchip Technology Inc.
DS39609B-page 31
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