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PIC18F6720 Datasheet

  • PIC18F6720

  • 64/80-Pin High-Performance,256 Kbit to 1 Mbit Enhanced Flash...

  • 3274.08KB

  • 380页

  • Microchip   Microchip

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PIC18F6520/8520/6620/8620/6720/8720
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Applicable Devices
Power-on Reset,
Brown-out Reset
---0 0000
MCLR Resets
WDT Reset
RESET
Instruction
Stack Resets
Wake-up via WDT
or Interrupt
---0 0000
---0 uuuu
(3)
TOSH
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
(3)
TOSL
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
(3)
STKPTR
PIC18F6X20 PIC18F8X20
00-0 0000
uu-0 0000
uu-u uuuu
(3)
PCLATU
PIC18F6X20 PIC18F8X20
---0 0000
---0 0000
---u uuuu
PCLATH
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
PCL
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
PC + 2
(2)
TBLPTRU
PIC18F6X20 PIC18F8X20
--00 0000
--00 0000
--uu uuuu
TBLPTRH
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
TBLPTRL
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
TABLAT
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
PRODH
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODL
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
INTCON
PIC18F6X20 PIC18F8X20
0000 000x
0000 000u
uuuu uuuu
(1)
INTCON2
PIC18F6X20 PIC18F8X20
1111 1111
1111 1111
uuuu uuuu
(1)
INTCON3
PIC18F6X20 PIC18F8X20
1100 0000
1100 0000
uuuu uuuu
(1)
INDF0
PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
POSTINC0 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
POSTDEC0 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
PREINC0
PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
PLUSW0
PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
FSR0H
PIC18F6X20 PIC18F8X20
---- xxxx
---- uuuu
---- uuuu
FSR0L
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1
PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
POSTINC1 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
POSTDEC1 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
PREINC1
PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
PLUSW1
PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
Legend:
u
= unchanged,
x
= unknown, - = unimplemented bit, read as 鈥?鈥?
q
= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1:
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2:
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3:
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4:
See Table 3-2 for Reset value for specific condition.
5:
Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read 鈥?鈥?
6:
Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read 鈥?鈥?
TOSU
PIC18F6X20 PIC18F8X20
DS39609B-page 32
铮?/div>
2004 Microchip Technology Inc.

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