PIC18F6720 Datasheet

  • PIC18F6720

  • 64/80-Pin High-Performance,256 Kbit to 1 Mbit Enhanced Flash...

  • 3274.08KB

  • 380页

  • Microchip   Microchip

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PIC18F6520/8520/6620/8620/6720/8720
TABLE 4-3:
File Name
TOSU
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
REGISTER FILE SUMMARY
Bit 7
鈥?/div>
Bit 6
鈥?/div>
Bit 5
鈥?/div>
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Details
POR, BOR on page:
---0 0000
0000 0000
0000 0000
Return Stack Pointer
Holding Register for PC<20:16>
00-0 0000
--10 0000
0000 0000
0000 0000
bit 21
(2)
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
TMR0IE
INTEDG1
INT3IE
INT0IE
INTEDG2
INT2IE
RBIE
INTEDG3
INT1IE
TMR0IF
TMR0IP
INT3IF
INT0IF
INT3IP
INT2IF
RBIF
RBIP
INT1IF
0000 0000
1111 1111
1100 0000
n/a
n/a
n/a
n/a
n/a
---- 0000
xxxx xxxx
xxxx xxxx
n/a
n/a
n/a
n/a
n/a
---- 0000
xxxx xxxx
Bank Select Register
---- 0000
n/a
n/a
n/a
32, 42
32, 42
32, 42
32, 43
32, 44
32, 44
32, 44
32, 64
32, 64
32, 64
32, 64
32, 85
32, 85
32, 89
32, 90
32, 91
57
57
57
57
57
32, 57
32, 57
32
57
57
57
57
57
33, 57
33, 57
33, 56
57
57
57
Top-of-Stack Upper Byte (TOS<20:16>)
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
STKFUL
鈥?/div>
STKUNF
鈥?/div>
鈥?/div>
bit 21
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
鈥?/div>
鈥?/div>
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
GIE/GIEH
RBPU
INT2IP
PEIE/GIEL
INTEDG0
INT1IP
Uses contents of FSR0 to address data memory 鈥?value of FSR0 not changed (not a physical register)
POSTINC0 Uses contents of FSR0 to address data memory 鈥?value of FSR0 post-incremented
(not a physical register)
POSTDEC0 Uses contents of FSR0 to address data memory 鈥?value of FSR0 post-decremented
(not a physical register)
PREINC0
PLUSW0
FSR0H
FSR0L
WREG
INDF1
Uses contents of FSR0 to address data memory 鈥?value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory 鈥?value of FSR0 pre-incremented
(not a physical register) 鈥?value of FSR0 offset by value in WREG
鈥?/div>
Working Register
Uses contents of FSR1 to address data memory 鈥?value of FSR1 not changed (not a physical register)
鈥?/div>
鈥?/div>
鈥?/div>
Indirect Data Memory Address Pointer 0 High Byte
Indirect Data Memory Address Pointer 0 Low Byte
POSTINC1 Uses contents of FSR1 to address data memory 鈥?value of FSR1 post-incremented
(not a physical register)
POSTDEC1 Uses contents of FSR1 to address data memory 鈥?value of FSR1 post-decremented
(not a physical register)
PREINC1
PLUSW1
FSR1H
FSR1L
BSR
INDF2
Uses contents of FSR1 to address data memory 鈥?value of FSR1 pre-incremented
(not a physical register)
Uses contents of FSR1 to address data memory 鈥?value of FSR1 pre-incremented
(not a physical register) 鈥?value of FSR1 offset by value in WREG
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Indirect Data Memory Address Pointer 1 High Byte
Indirect Data Memory Address Pointer 1 Low Byte
Uses contents of FSR2 to address data memory 鈥?value of FSR2 not changed (not a physical register)
POSTINC2 Uses contents of FSR2 to address data memory 鈥?value of FSR2 post-incremented
(not a physical register)
POSTDEC2 Uses contents of FSR2 to address data memory 鈥?value of FSR2 post-decremented
(not a physical register)
Legend:
Note 1:
2:
3:
x
= unknown,
u
= unchanged, 鈥?= unimplemented,
q
= value depends on condition
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read 鈥?鈥?in all other oscillator
modes.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
These registers are unused on PIC18F6X20 devices; always maintain these clear.
DS39609B-page 52
铮?/div>
2004 Microchip Technology Inc.

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