鈥?/div>
Intermediate computational values
Local variables of subroutines
Faster context saving/switching of variables
Common variables
Faster evaluation/control of SFRs (no banking)
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into sixteen banks. When using direct
addressing, the BSR should be configured for the
desired bank.
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read 鈥?鈥檚 and
writes will have no effect.
A
MOVLB
instruction has been provided in the
instruction set to assist in selecting banks.
If the currently selected bank is not implemented, any
read will return all 鈥?鈥檚 and all writes are ignored. The
Status register bits will be set/cleared as appropriate for
the instruction performed.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A
MOVFF
instruction ignores the BSR, since the 12-bit
addresses are embedded into the instruction word.
Section 4.12 鈥淚ndirect Addressing, INDF and FSR
Registers鈥?/span>
provides a description of indirect address-
ing, which allows linear addressing of the entire RAM
space.
The Access Bank is comprised of the upper 160 bytes
in Bank 15 (SFRs) and the lower 96 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 4-7
indicates the Access RAM areas.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in
the Access Bank. This bit is denoted by the 鈥榓鈥?bit (for
access bit).
When forced in the Access Bank (a =
0),
the last
address in Access RAM Low is followed by the first
address in Access RAM High. Access RAM High maps
the Special Function Registers, so that these registers
can be accessed without any software overhead. This is
useful for testing status flags and modifying control bits.
FIGURE 4-8:
DIRECT ADDRESSING
Direct Addressing
BSR<3:0>
7
From Opcode
(3)
0
Bank Select
(2)
Location Select
(3)
00h
000h
01h
100h
0Eh
E00h
0Fh
F00h
Data
Memory
(1)
0FFh
1FFh
EFFh
FFFh
Bank 0
Note 1:
2:
3:
For register file map detail, see Table 4-2.
Bank 1
Bank 14
Bank 15
The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the
registers of the Access Bank.
The
MOVFF
instruction embeds the entire 12-bit address in the instruction.
DS39609B-page 56
铮?/div>
2004 Microchip Technology Inc.
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