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PIC18F6720 Datasheet

  • PIC18F6720

  • 64/80-Pin High-Performance,256 Kbit to 1 Mbit Enhanced Flash...

  • 3274.08KB

  • 380页

  • Microchip   Microchip

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PIC18F6520/8520/6620/8620/6720/8720
5.2.2
TABLAT 鈥?TABLE LATCH REGISTER
5.2.4
TABLE POINTER BOUNDARIES
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch is used to hold
8-bit data during data transfers between program
memory and data RAM.
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a
TBLRD
is executed, all 22 bits of the Table
Pointer determine which byte is read from program
memory into TABLAT.
When a
TBLWT
is executed, the three LSbs of the Table
Pointer (TBLPTR<2:0>) determine which of the eight
program memory holding registers is written to. When
the timed write to program memory (long write) begins,
the 19 MSbs of the Table Pointer, TBLPTR
(TBLPTR<21:3>), will determine which program mem-
ory block of 8 bytes is written to. For more detail, see
Section 5.5 鈥淲riting to Flash Program Memory鈥?
When an erase of program memory is executed, the
16 MSbs of the Table Pointer (TBLPTR<21:6>) point to
the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.
Figure 5-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
5.2.3
TBLPTR 鈥?TABLE POINTER
REGISTER
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order 21
bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the Device ID, the User ID and the configuration bits.
The Table Pointer, TBLPTR, is used by the
TBLRD
and
TBLWT
instructions. These instructions can update the
TBLPTR in one of four ways, based on the table oper-
ation. These operations are shown in Table 5-1. These
operations on the TBLPTR only affect the low-order
21 bits.
TABLE 5-1:
TABLE POINTER OPERATIONS WITH
TBLRD
AND
TBLWT
INSTRUCTIONS
Operation on Table Pointer
TBLPTR is not modified
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
Example
TBLRD*
TBLWT*
TBLRD*+
TBLWT*+
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
FIGURE 5-3:
21
TABLE POINTER BOUNDARIES BASED ON OPERATION
TBLPTRU
16
15
TBLPTRH
8
7
TBLPTRL
0
ERASE
鈥?/div>
TBLPTR<20:6>
WRITE
鈥?/div>
TBLPTR<21:3>
READ
鈥?/div>
TBLPTR<21:0>
DS39609B-page 64
铮?/div>
2004 Microchip Technology Inc.

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