PIC18F6720 Datasheet

  • PIC18F6720

  • 64/80-Pin High-Performance,256 Kbit to 1 Mbit Enhanced Flash...

  • 3274.08KB

  • 380页

  • Microchip   Microchip

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PIC18F6520/8520/6620/8620/6720/8720
REGISTER 9-9:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
U-0
鈥?/div>
bit 7
bit 7-6
bit 5
Unimplemented:
Read as 鈥?鈥?/div>
RC2IE:
USART2 Receive Interrupt Enable bit
1
= Enables the USART2 receive interrupt
0
= Disables the USART2 receive interrupt
TX2IE:
USART2 Transmit Interrupt Enable bit
1
= Enables the USART2 transmit interrupt
0
= Disables the USART2 transmit interrupt
TMR4IE:
TMR4 to PR4 Match Interrupt Enable bit
1
= Enables the TMR4 to PR4 match interrupt
0
= Disables the TMR4 to PR4 match interrupt
CCPxIE:
CCPx Interrupt Enable bit (CCP Modules 3, 4 and 5)
1
= Enables the CCPx interrupt
0
= Disables the CCPx interrupt
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
鈥?鈥?= Bit is set
U = Unimplemented bit, read as 鈥?鈥?/div>
鈥?鈥?= Bit is cleared
x = Bit is unknown
U-0
鈥?/div>
R/W-0
RC2IE
R/W-0
TX2IE
R/W-0
TMR4IE
R/W-0
CCP5IE
R/W-0
CCP4IE
R/W-0
CCP3IE
bit 0
bit 4
bit 3
bit 2-0
铮?/div>
2004 Microchip Technology Inc.
DS39609B-page 97

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