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AD8045ACP-REEL7 Datasheet

  • AD8045ACP-REEL7

  • Analog Devices [3 nV/Hz Ultralow Distortion, High Speed Op ...

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AD8045
EXPOSED PADDLE
The AD8045 features an exposed paddle, which lowers the
thermal resistance by 25% compared to a standard SOIC plastic
package. The exposed paddle of the AD8045 is internally con-
nected to the negative power supply pin. Therefore, when laying
out the board, the exposed paddle must either be connected to
the negative power supply or left floating (electrically isolated).
Soldering the exposed paddle to the negative power supply metal
ensures maximum thermal transfer. Figure 74 and Figure 75 show
the proper layout for connecting the SOIC and LFCSP exposed
paddle to the negative supply.
THERMAL CONDUCTIVE INSULATOR
04814-0-072
Figure 76. SOIC with Thermal Conductive Pad Material
The thermal pad provides high thermal conductivity but
isolates the exposed paddle from ground or other potential. It is
recommended, when possible, to solder the paddle to the nega-
tive power supply plane or trace for maximum thermal transfer.
Note that soldering the paddle to ground shorts the negative
power supply to ground and can cause irreparable damage to
the AD8045.
DRIVING CAPACITIVE LOADS
04814-0-071
Figure 74. SOIC Exposed Paddle Layout
The use of thermal vias or 鈥渉eat pipes鈥?can also be incorporated
into the design of the mounting pad for the exposed paddle.
These additional vias help to lower the overall theta junction to
ambient (胃
JA
). Using a heavier weight copper on the surface to
which the amplifier鈥檚 exposed paddle is soldered can greatly
reduce the overall thermal resistance 鈥渟een鈥?by the AD8045.
In general, high speed amplifiers have a difficult time driving
capacitive loads. This is particularly true in low closed-loop
gains, where the phase margin is the lowest. The difficulty arises
because the load capacitance, C
L
, forms a pole with the output
resistance, R
O
, of the amplifier. The pole can be described by the
equation
f
P
=
1
2蟺
R
O
C
L
If this pole occurs too close to the unity gain crossover point,
the phase margin degrades. This is due to the additional phase
loss associated with the pole.
The AD8045 output can drive 18 pF of load capacitance directly,
in a gain of +2 with 30% overshoot, as shown in Figure 37.
Larger capacitance values can be driven but must use a snub-
bing resistor (R
SNUB
) at the output of the amplifier, as shown in
Figure 61 and Figure 62. Adding a small series resistor, R
SNUB
,
creates a zero that cancels the pole introduced by the load
capacitance. Typical values for R
SNUB
can range from 25 鈩?to
50 鈩? The value is typically arrived at empirically and based on
the circuit requirements.
Figure 75. LFCSP Exposed Paddle Layout
For existing designs that want to incorporate the AD8045,
electrically isolating the exposed paddle is another option. If the
exposed paddle is electrically isolated, the thermal dissipation is
primarily through the leads, and the thermal resistance of the
package now approaches 125掳C/W, the standard SOIC 胃
JA
.
However, a thermally conductive and electrically isolated pad
material may be used. A thermally conductive spacer, such as
the Bergquist Company鈥檚 Sil-Pad, is an excellent solution to this
problem. Figure 76 shows a typical implementation using
thermal pad material.
04814-0-073
Rev. A | Page 23 of 24

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