AT24C01A/02/04/08A/16A
Bus Timing
Figure 2.
SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
Figure 3.
SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
8th BIT
WORDn
ACK
twr
STOP
CONDITION
(1)
START
CONDITION
Note:
1. The write cycle time t
WR
is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
Figure 4.
Data Validity
7
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