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CS5954AM Datasheet

  • CS5954AM

  • Cypress Semiconductor [USB Controller for NAND Flash]

  • 411.34KB

  • CYPRESS

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ADVANCE
INFORMATION
CS5954AM
In addition, there is space for an optional three bit immediate value, which is used in a manner appropriate to the instruction. The
destination field functions exactly as it does in the dual operand operation instructions.
SHR
bit:
15
14
13
12
1101000
destination:= destination >> count
Flags Affected: Z, C, S
SHL
bit:
15
14
13
12
1101001
destination:= destination << count
Flags Affected: Z, C, S
[37, 38]
ROR
bit:
15
14
13
12
1101010
11
10
9
8
7
count-1
6
5
4
3
2
1
0
destination
11
10
9
8
7
count-1
6
5
4
3
2
1
0
destination
11
10
9
8
7
count-1
6
5
4
3
2
1
0
destination
Works identically to the SHR instruction, except that the LSB of
destination
is rotated into the MSB, as opposed to SHR, which
discards that bit
Flags Affected: Z, C, S
[39]
ROL
bit:
15
14
13
12
1101011
11
10
9
8
7
count-1
6
5
4
3
2
1
0
destination
Works identically to the SHL instruction, except that the MSB of
destination
is rotated into the LSB, as opposed to SHL, which
discards that bit
Flags Affected: Z, C, S
ADDI
bit:
15
14
13
12
1101100
destination:= destination + n
Flags Affected: Z, S
SUBI
bit:
15
14
13
12
1101101
destination:= destination 鈥?n
Flags Affected: Z, S
NOT
bit:
15
14
13
12
1101111
destination:= ~destination
Flags Affected: Z, S
NEG
bit:
15
14
13
12
1101111
Notes:
37. The SHR instruction shifts in sign bits.
38. The C flag is set with last bit shifted out of LSB.
39. The C flag is set with last bit shifted out of MSB.
11
10
9
8
7
n-1
6
5
4
3
2
1
0
destination
11
10
9
8
7
n-1
6
5
4
3
2
1
0
destination
11
10
9
8
7
000
6
5
4
3
2
1
0
destination
(bitwise 1鈥檚 complement negation)
11
10
9
8
7
001
6
5
4
3
2
1
0
destination
Document #: 38-08025 Rev. **
Page 34 of 44

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