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CS8416-CS Datasheet

  • CS8416-CS

  • Cirrus Logic [192 kHZ DIGITAL AUDIO INTERFACE RECEIVER]

  • 764.03KB

  • CIRRUS

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CS8416
The error bits are 鈥渟ticky鈥? they are set on the first
occurrence of the associated error and will remain
set until the user reads the register through the con-
trol port. This enables the register to log all un-
masked errors that occurred since the last time the
register was read.
As a result of the bits 鈥渟tickiness鈥? it is necessary to
perform two reads on these registers to see if the er-
ror condition still exists.
The Receiver Error Mask register (06h) allows
masking of individual errors. The bits in this regis-
ter default to 00h and serve as masks for the corre-
sponding bits of the Receiver Error register. If a
mask bit is set to 1, the error is unmasked, which
implies the following: its occurrence will be report-
ed in the receiver error register, induce a pulse on
RERR, invoke the occurrence of a RERR interrupt,
and affect the current audio sample according to the
status of the HOLD bits. The exceptions are the
QCRC and CCRC errors, which do not affect the
current audio sample, even if unmasked.
The HOLD bits allow a choice of:
鈥?Holding the previous sample
鈥?/div>
OR
鈥?/div>
Not changing the current audio sample
RERR 鈥?The logical OR of all unmasked receiver
error bits, not 鈥榮ticky鈥? RERR may be selected for
output on a GPO pin.
NVERR 鈥?Non-Validity Receiver error
Hardware Mode
In Hardware mode the user may choose between
NVERR or RERR by pulling the NV/RERR pin
low or high respectively.
Replacing the current sample with zero (mute)
19h - 22h. Registers 19h - 1Dh contain the A chan-
nel status data. Registers 1Eh - 22h contain the B
channel status data.
The EMPH, C, and U bits may be selected on GPO
pins by appropriately setting the GPOxSEL bits in
control port registers 02h and 03h.
The encoded channel status bits which indicate
sample word length are decoded according to
AES3-1992 or IEC 60958. The number of auxiliary
bits are reported in bits 7 to 4 of the Receiver Chan-
nel Status register.
Appendix B describes the overall handling of
Channel Status and User data.
5.5
User Data Handling
Received User data may also be output to the U pin
under the control of a control register bit. VLRCK
(a virtual word clock, available through GPO pins,
that can used to frame the C/U output) and OLRCK
in serial port master mode can be made available to
qualify the U data output in software mode.
Figure 9
illustrates the timing. In hardware mode,
only OLRCK in master mode is available to qualify
the U output. If the incoming user data bits have
been encoded as Q- channel subcode, the data is de-
coded, buffered, and presented in 10 consecutive
register locations. An interrupt may be enabled to
indicate the decoding of a new Q-channel block,
which may be read through the control port.
5.5.1
Non-Audio Auto-Detection
5.4
Channel Status Data Handling
Software Mode
The first 5 bytes of the Channel Status block are de-
coded into the Receiver Channel Status Registers
18
An AES3 data stream may be used to convey non-
audio data, thus it is important to know whether the
incoming AES3 data stream is digital audio or not.
This information is typically conveyed in channel
status bit 1 (AUDIO), which is extracted automati-
cally by the CS8416. However, certain non-audio
sources, such as AC-3 or MPEG encoders, may not
adhere to this convention, and the bit may not be
properly set. The CS8416 AES3 receiver can detect
such non-audio data through the use of an autode-
tect module. The autodetect module is similar to
DS578PP2

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