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CS8416-CS Datasheet

  • CS8416-CS

  • Cirrus Logic [192 kHZ DIGITAL AUDIO INTERFACE RECEIVER]

  • 764.03KB

  • CIRRUS

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CS8416
0 - Serial audio output port is in slave mode
1 - Serial audio output port is in master mode
SOSF - OSCLK frequency (for master mode)
Default = 鈥?鈥?/div>
0 - 64*Fs
1 - 128*Fs
SORES[1:0] - Resolution of the output data on SDOUT
Default = 鈥?0鈥?/div>
00 - 24-bit resolution
01 - 20-bit resolution
10 - 16-bit resolution
11 - Direct copy of the received NRZ data from the AES3 receiver including C, U, and V bits. The time
slot occupied by the Z bit is used to indicate the location of the block start. This setting forces the
SOJUST bit to be 鈥?鈥?
SOJUST - Justification of SDOUT data relative to OLRCK
Default = 鈥?鈥?/div>
0 - Left-justified
1 - Right-justified (master mode only and SORES
鈮?1)
SODEL - Delay of SDOUT data relative to OLRCK, for left-justified data formats
(This control is only valid in left justified mode)
Default = 鈥?鈥?/div>
0 - MSB of SDOUT data occurs in the first OSCLK period after the OLRCK edge
1 - MSB of SDOUT data occurs in the second OSCLK period after the OLRCK edge
SOSPOL - OSCLK clock polarity
Default = 鈥?鈥?/div>
0 - SDOUT sampled on rising edges of OSCLK
1 - SDOUT sampled on falling edges of OSCLK
SOLRPOL - OLRCK clock polarity
Default = 鈥?鈥?/div>
0 - SDOUT data is for the left channel when OLRCK is high
1 - SDOUT data is for the right channel when OLRCK is high
28
DS578PP2

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