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CS8416-CS Datasheet

  • CS8416-CS

  • Cirrus Logic [192 kHZ DIGITAL AUDIO INTERFACE RECEIVER]

  • 764.03KB

  • CIRRUS

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CS8416
8.15
OMCK/RMCK Ratio (18h)
6
ORR6
5
ORR5
4
ORR4
3
ORR3
2
ORR2
1
ORR1
0
ORR0
7
ORR7
This register allows the calculation of the incoming sample rate by the host microcontroller from the
equation ORR=Fso/Fsi. The Fso is determined by OMCK, whose frequency is assumed to be 256
Fso. ORR is represented as an unsigned 2-bit integer and a 6-bit fractional part. The value is mean-
ingful only after the PLL has reached lock. For example, if the OMCK is 12.288MHz, Fso would be
48KHz (48KHz = 12.288MHz/256). Then if the input sample rate is also 48KHz, you would get 1.0
from the ORR register.(The value from the ORR register is hexadecimal, so the actual value you will
get is 40h). If F
SO
/F
SI
>
3
63
/
64
, ORR will saturate at the value FFh. Also, there is no hysteresis on
ORR. Therefore a small amount of jitter on either clock can cause the LSB ORR[0] to oscillate.
ORR[7:6] - Integer part of the ratio (Integer value=Integer(SRR[7:6]))
ORR[5:0] - Fractional part of the ratio (Fraction value=Integer(SRR[5:0])/64)
8.16
25
26
27
28
29
30
31
32
33
34
Channel Status Registers (19h - 22h)
Channel A Status Byte 0
Channel A Status Byte 1
Channel A Status Byte 2
Channel A Status Byte 3
Channel A Status Byte 4
Channel B Status Byte 0
Channel B Status Byte 1
Channel B Status Byte 2
Channel B Status Byte 3
Channel B Status Byte 4
AC0[7]
AC1[7]
AC2[7]
AC3[7]
AC4[7]
BC0[7]
BC1[7]
BC2[7]
BC3[7]
BC4[7]
AC0[6]
AC1[6]
AC2[6]
AC3[6]
AC4[6]
BC0[6]
BC1[6]
BC2[6]
BC3[6]
BC4[6]
AC0[5]
AC1[5]
AC2[5]
AC3[5]
AC4[5]
BC0[5]
BC1[5]
BC2[5]
BC3[5]
BC4[5]
AC0[4]
AC1[4]
AC2[4]
AC3[4]
AC4[4]
BC0[4]
BC1[4]
BC2[4]
BC3[4]
BC4[4]
AC0[3]
AC1[3]
AC2[3]
AC3[3]
AC4[3]
BC0[3]
BC1[3]
BC2[3]
BC3[3]
BC4[3]
AC0[2]
AC1[2]
AC2[2]
AC3[2]
AC4[2]
BC0[2]
BC1[2]
BC2[2]
BC3[2]
BC4[2]
AC0[1]
AC1[1]
AC2[1]
AC3[1]
AC4[1]
BC0[1]
BC1[1]
BC2[1]
BC3[1]
BC4[1]
AC0[0]
AC1[0]
AC2[0]
AC3[0]
AC4[0]
BC0[0]
BC1[0]
BC2[0]
BC3[0]
BC4[0]
8.17
35
36
37
38
IEC61937 PC/PD Burst preamble (23h - 26h)
Burst Preamble PC Byte 0
Burst Preamble PC Byte 1
Burst Preamble PD Byte 0
Burst Preamble PD Byte 1
PC0[7]
PC1[7]
PD0[7]
PD1[7]
PC0[6]
PC1[6]
PD0[6]
PD1[6]
PC0[5]
PC1[5]
PD0[5]
PD1[5]
PC0[4]
PC0[4]
PC0[4]
PD1[4]
PC0[3]
PC1[3]
PD0[3]
PD1[3]
PC0[2]
PC1[2]
PD0[2]
PD1[2]
PC0[1]
PC1[1]
PD0[1]
PD1[1]
PC0[0]
PC1[0]
PD0[0]
PD1[0]
8.18
CS8416 I.D. and Version Register (7Fh)
7
ID3
6
ID2
5
ID1
4
ID0
3
VER3
2
VER2
1
VER1
0
VER0
ID[3:0]= 0010
VER[3:0] = 0001 (revision A)
DS578PP2
33

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