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CS8416-CS Datasheet

  • CS8416-CS

  • Cirrus Logic [192 kHZ DIGITAL AUDIO INTERFACE RECEIVER]

  • 764.03KB

  • CIRRUS

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CS8416
9. PIN DESCRIPTION - SOFTWARE MODE
RXP3
RXP2
RXP1
RXP0
RXN
VA+
AGND
FILT
RST
RXP4
RXP5
RXP6
RXP7
AD0/CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OLRCK
OSCLK
SDOUT
OMCK
RMCK
VD+
DGND
VL+
GPO0
GPO1
AD2/GPO2
SDA/CDOUT
SCL/CCLK
AD1/CDIN
RXP[7:0]
13
12
11
10
1
2
3
4
5
Additional AES3/SPDIF Receiver Port
(
Input
) - Single-ended receiver inputs carrying AES3 or
S/PDIF digital data. These inputs comprise the 8:2 S/PDIF Input Multiplexer. The select line control is
accessed using the Control 4 register. Please note that any unused inputs can be left floating or tied to
ground. See Appendix A for recommended input circuits.
RXN
AES/SPDIF input
- Used along with RXP[X] to form an AES3 differential input. In single-ended
operation this should be capacitively coupled to ground.
Positive Analog Power
- Positive supply for the analog section. Nominally +3.3 V. This supply should
be as quiet as possible since noise on this pin will directly affect the jitter performance of the recovered
clock
Positive Digital Power
鈥?Nominally 3.3 V
Positive 鈥?Interface Power
鈥?3.3 V to 5.0 V: this supply sets the CS8416 I/O levels, including RXPx &
RXN
Analog Ground
- Ground for the analog circuitry in the chip. AGND and DGND should be con nected
to a common ground area under the chip.
Digital & I/O Ground
PLL Loop Filter
(
Output
) - An RC network should be connected between this pin and analog ground.
For minimum PLL jitter, return the ground end of the filter network directly to AGND
VA+
6
VD+
VL+
AGND
23
21
6
DGND
FILT
22
8
DS578PP2
35

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