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EN29LV640 Datasheet

  • EN29LV640

  • Eon Silicon Solution Inc. [64 Megabit (4M x 16-bit ) CMOS 3...

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  • EON

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EN29LV640
Hardware Data protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes as seen in the Command Definitions table. Additionally, the
following hardware data protection measures prevent accidental erasure or programming, which
might otherwise be caused by false system level signals during Vcc power up and power down
transitions, or from system noise.
Low V
CC
Write Inhibit
B
B
When V
CC
is less than V
LKO
, the device does not accept any write cycles. This protects data during
V
CC
power up and power down. The command register and all internal program/erase circuits are
disabled, and the device resets. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The
system must provide the proper signals to the control pins to prevent unintentional writes when V
CC
is greater than V
LKO
.
B
B
B
B
B
B
Write Pulse 鈥淕litch鈥?protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V
IL
, CE# = V
IH
, or WE# = V
IH
. To initiate a
write cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE#
are all logical zero (not recommended usage), it will be considered a read.
B
B
B
B
B
B
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even
with CE# = V
IL
, WE#= V
IL
and OE# = V
IH
, the device will not accept commands on the rising edge of
WE#.
B
B
B
B
B
B
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
17
漏2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2007/01/23

EN29LV640 PDF文件相关型号

EN29LV640H-90BCP,EN29LV640H-90BI

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