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EN29LV640 Datasheet

  • EN29LV640

  • Eon Silicon Solution Inc. [64 Megabit (4M x 16-bit ) CMOS 3...

  • 423.46KB

  • EON

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EN29LV640
Just prior to the completion of the embedded operations, DQ7 may change asynchronously when
the output enable (OE#) is low. This means that the device is driving status information on DQ7 at
one instant of time and valid data at the next instant of time. Depending on the time the system
samples the DQ7 output, it may read the status of valid data. Even if the device has completed the
embedded operation and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid.
The valid data on DQ0-DQ7 should be read on the subsequent read attempts.
The flowchart for DATA# Polling (DQ7) is shown on Flowchart 4. The DATA# Polling (DQ7) timing
diagram is shown in Figure 6.
RY/BY#: Ready/Busy Status output
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is
in progress or completed. The RY/BY# status is valid after the rising edge of the final WE# pulse in
the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied
together in parallel with a pull-up resistor to V
CC
.
In the output-low period, signifying Busy, the device is actively erasing or programming. This
includes programming in the Erase Suspend mode. If the output is high, signifying the Ready, the
device is ready to read array data (including during the Erase Suspend mode), or is in the standby
mode.
DQ6: Toggle Bit I
The device provides a 鈥淭oggle Bit鈥?on DQ6 to indicate the status of the embedded programming and
erase operations. (See Table 10)
During an embedded Program or Erase operation, successive attempts to read data from the device
at any address (by active OE# or CE#) will result in DQ6 toggling between 鈥渮ero鈥?and 鈥渙ne鈥? Once
the embedded Program or Erase operation is completed, DQ6 will stop toggling and valid data will
be read on the next successive attempts. During Programming, the Toggle Bit is valid after the rising
edge of the fourth WE# pulse in the four-cycle sequence. During Erase operation, the Toggle Bit is
valid after the rising edge of the sixth WE# pulse for sector erase or chip erase.
In embedded programming, if the sector being written to is protected, DQ6 will toggles for about 2
渭s,
then stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all
selected sectors are protected, DQ6 will toggle for about 100
渭s.
The chip will then return to the read
mode without changing data in all protected sectors.
The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 5. The Toggle Bit timing diagram is
shown in Figure 7
.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count
limit. Under these conditions DQ5 produces a 鈥?.鈥?This is a failure condition that indicates the
program or erase cycle was not successfully completed. Since it is possible that DQ5 can become a
1 when the device has successfully completed its operation and has returned to read mode, the user
must check again to see if the DQ6 is toggling after detecting a 鈥?鈥?on DQ5.
The DQ5 failure condition may appear if the system tries to program a 鈥?鈥?to a location that is
previously programmed to 鈥?.鈥?/div>
Only an erase operation can change a 鈥?鈥?back to a 鈥?.鈥?/div>
Under
this condition, the device halts the operation, and when the operation has exceeded the timing limits,
DQ5 produces a 鈥?.鈥?Under both these conditions, the system must issue the reset command to
return the device to reading array data.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
22
漏2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2007/01/23

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EN29LV640H-90BCP,EN29LV640H-90BI

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