您的位置：维库电子市场网 > Datasheet > CS493112-CL

CS493112-CL Datasheet

  • CS493112-CL

  • Multi-Standard Audio Decoder Family

  • 1338.66KB

  • CIRRUS

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

CS49300 Family DSP
byte, and the host should poll the Host Control
Register again. If HINBSY is low, then the host
may write a control byte into the Host Message
Register.
3) The host knows that the DSP is ready for a new
control byte at this point and should write the
control byte to the Host Message Register
(A[1:0] = 00b).
4) If the host would like to write any more control
bytes to the CS493XX, the host should once
again poll the Host Control Register (return to
step 1).
byte response from the DSP. The host must read the
response byte and act accordingly. The boot
procedure is discussed in
Section 8.1, 鈥淗ost Boot鈥?/span>
on page 52.
During regular operation (at run-time), the
responses from the CS493XX will always be 6
bytes in length.
The example shown in this section can be used for
any control read situation. The generic function
鈥楻ead_Byte_*()鈥?is used in the following example
as
a
generalized
reference
to
either
Read_Byte_MOT()
or
Read_Byte_INT().
Figure 29
shows a typical read sequence. The
protocol presented in
Figure 29
will now be
described in detail.
1) Optionally, INTREQ going low may be used as
an interrupt to the host to indicate that the
CS493XX has an outgoing message. Even with
the use of INTREQ, HOUTRDY must be
checked to insure that bytes are ready for the
host during the read process. Please note that
INTREQ does not go low to indicate an
outgoing message during boot.
2) The host reads the Host Control Register
(A[1:0] = 01b) in order to determine the state of
the communication interface. Please note that
鈥楻ead_Byte_*()鈥?is a generalized reference to
either
Read_Byte_MOT()
or
Read_Byte_INT().
3) In order to determine whether the CS493XX
has an outgoing control byte that is valid, the
host must check the HOUTRDY bit of the Host
Control Register (bit 1). If HOUTRDY is high,
then the Host Message Register contains a valid
message byte for the host. If HOUTRDY is
low, then the DSP has not placed a new control
byte in the Host Message Register, and the host
should poll the Host Control Register again.
4) The host knows that the DSP is ready to
provide a new response byte at this point. The
6.2.3.2.Control Read in a Parallel Host Mode
When reading control data from the CS493XX, the
same protocol is used whether the host is reading a
single byte or a 6 byte message.
During the boot procedure, a handshaking protocol
is used by the CS493XX. This handshake consists
of a 3 byte write to the CS493XX followed by a 1
READ_BYTE_*(HOST CONTROL REGISTER)
YES
HINSBY==1
NO
WRITE_BYTE_*(HOST MESSAGE REGISTER)
YES
MORE BYTES
TO WRITE?
NO
FINISHED
Figure 28. Typical Parallel Host Mode Control
Write Sequence Flow Diagram
DS339PP4
47

CS493112-CL相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2025 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：
技术客服：

0571-85317607

网站技术支持

13606545031

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！