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CS493112-CL Datasheet

  • CS493112-CL

  • Multi-Standard Audio Decoder Family

  • 1338.66KB

  • CIRRUS

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CS49300 Family DSP
ROM Content
CS493254
N/A, All IBA codes are loaded
using Host Boot technique
Dolby Digital with PLII +
Cinema Re-EQ,
HDCD
Image Size
Number of Pages
Required
IBA Code(s)
Stored in Host
Type of Design
N/A, All IBA codes
N/A, All IBA codes Dolby Digital with Dolby Digital with
are loaded using
are loaded using
PL II,
Pro Logic II 5.1
Host Boot technique Host Boot technique
C.O.S.
Channel System
32 + 32 = 64 Kbytes
2
C.O.S.
Enhanced
Dolby Digital with
Pro Logic II 5.1
Channel System
N/A, All IBA codes
N/A, All IBA codes Dolby Digital with
Enhanced
are loaded using
are loaded using
PL II,
Dolby Digital/
Host Boot technique Host Boot technique
C.O.S., DTS
DTS 5.1 Channel
System
Dolby Digital with C.E.S., MPEG
32 * 4 pages =
4
C.O.S.
Basic 6.1
Multichannel with C.E.S., DTS
128 Kbytes
Channel System
with C.E.S., MP3
Dolby Digital with PLII with
32 * 4 pages =
4
C.O.S.
Enhanced 6.1
C.E.S., MPEG Multichannel with
128 Kbytes
Channel System
PLII, DTS-ES, DTS Neo:6
32 * 8 =
8
C.O.S.
Premium
Dolby Digital with PLII with
256 Kbytes
6.1/7.1 Channel
C.E.S., MPEG Multichannel with
System
PLII, DTS-ES with PLII, DTS
Neo:6, HDCD, LOGIC7, MP3,
Virtual Dolby Digital with VMAx
VirtualTheater
CS493292
Premium 6.1/7.1
32 * 8 =
8
N/A, No IBA
Dolby Digital with PLII with
256 Kbytes
Codes not avail- Channel System
C.E.S., MPEG Multichannel with
with AAC
able for the
PLII, DTS-ES, DTS Neo:6,
Support
CS493292
HDCD, SRS Circle Surround II,
C.O.S., MPEG-2: AAC
Table 12. Memory Requirements for Example 5.1, 6.1 and 7.1 Channel Systems
CS493264
N/A, All IBA codes are loaded
using Host Boot technique
require external SRAM. Please refer to the
CS4932X/CS49330 Part Matrix vs. Code Matrix
for more detail about each particular application
code.
The speed of external ROM or Flash Memory need
only be 330nS (or faster) which stores the
application codes, while the speed of the SRAM
must be 70nS or faster.
8.7. External Memory Examples
8.7.1. Non-Paged Autoboot Memory
The most rudimentary memory design discussed
above is the non-paged memory. In a non-paged
design, the DSP can only access one item in
memory which could be either a single full
download code load. The memory image given in
Figure 40 is an example of a non-paged memory
image.
Only 15 of the 16 output bits of the address latches
would be connected to address bits A0-A14 of the
DS339PP4
63

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