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CS493112-CL Datasheet

  • CS493112-CL

  • Multi-Standard Audio Decoder Family

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  • CIRRUS

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CS49300 Family DSP
is presented most significant bit first. It should be
noted that in the multichannel modes the SCLK
rate must be greater than the number of bits per
channel multiplied by the number of channels. In
the example SCLK must be greater than M * 6.
Because each of the ports is fully configurable
(SCLK polarity, LRCLK polarity, Word Width,
SCLK Rate) not all modes have been presented.
names, mnemonics and pin numbers associated
with the DAI.
Pin Name
SDATAN1
STCCLK2
SCLKN1
LRCLKN1
Pin Description
Serial Data In
Secondary STC clock
Serial Bit Clock
Frame Clock
Pin Number
22
25
26
Table 13. Digital Audio Input Port
10.2. Digital Audio Input Port
The digital audio input port, or DAI, is used for
both compressed and PCM digital audio data input.
In addition this port supports a special clocking
mode in which a clock can be input to directly drive
the internal 33 bit counter.
Table 13, 鈥淒igital
Audio Input Port,鈥?on page 68
shows the pin
The DAI is fully configurable including support for
I
2
S, left justified and multichannel formats. In
addition the DAI can be programmed for slave
clocks, where LRCLKN1 and SCLKN1 are inputs,
or master clocks, where LRCLKN1 and SCLKN1
are outputs. In order for clocks to be master, the
internal PLL must be used.
STCCLK2 can also be programmed to drive the
internal 33 bit counter. This counter would
typically be driven by a 90kHz clock. The internal
LR C K
SCLK
SDATA
MSB
Le ft
R ig ht
LSB
M SB
LS B
Figure 43. I
2
S Format
LRCK
SC LK
SDATA
M SB
Le ft
R ig ht
LS B
MSB
LS B
MSB
Figure 44. Left Justified Format (Rising Edge Valid SCLK)
LR C LK
S C LK
SDATA
MSB
LSB
M SB
LS B
MSB
LS B
MSB
LS B
MSB
LS B
MSB
L SB
MSB
M C locks
P er C hannel
M Clocks
P er Channel
M C lock s
P er C h annel
M C locks
P er C hann el
M C lock s
P er C hannel
M Clocks
P er Ch annel
Figure 45. Multichannel Format
68
DS339PP4

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