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LC5256MC-5F256C Datasheet

  • LC5256MC-5F256C

  • Lattice Semiconductor [3.3V, 2.5V and 1.8V In-System Progra...

  • 427.20KB

  • LATTICE   LATTICE

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Lattice Semiconductor
Pseudo Dual-Port SRAM Mode
ispXPLD 5000MX Family Data Sheet
In Pseudo Dual-Port SRAM Mode the multi-function array is con铿乬ured as a SRAM with an independent read and
write ports that access the same 16,384-bits of memory. Data widths of 1, 2, 4, 8, 16 and 32 are supported by the
MFB. Figure 10 shows the block diagram of the Pseudo Dual-Port SRAM.
Write data, write address, chip select and write enable signals are always synchronous (registered). The read data
and read address signals can be synchronous or asynchronous. Reset is asynchronous. All write signals share the
same clock, and clock enable. All read signals share the same clock and clock enable. Reset is shared by both
read and write signals. Table 6 shows the possible sources for the clock, clock enable and initialization signals for
the various registers.
Figure 10. Pseudo Dual-Port SRAM Block Diagram
CLK0
CLK1
CLK2
CLK3
RESET
Read Address
(RAD[0:8-13])
Read Data
(RD[0:0-15])
Write Address
(WAD[0:8-13])
68 Inputs
From
Routing
16,384 bit
Pseudo
鈥?/div>
Dual
Write Enable
(WE)
鈥?/div>
Port
Write Clock
(WCLK)
SRAM
Write Chip Sel
(WCS[0,1])
Array
(WD[0:0,1,3,7,15,31])
Write Data
Write Clk Enable
(WCEN)
Read Clk Enable
(RCEN)
Read Clock
(RCLK)
Reset
(RST)
Table 6. Register Clock, Clock Enable, and Reset in Pseudo Dual-Port SRAM Mode
Register
Input
Clock
Write Address, Write
Clock Enable
Data, Write Enable,
and Write Chip Select
Reset
Clock
Read Data and Read Clock Enable
Address
Reset
Source
WCLK or one of the global clocks (CLK0 - CLK3). The selected signal can
be inverted if desired.
WCEN or one of the global clocks (CLK1 - CLK2). The selected signal can
be inverted if desired.
Created by the logical OR of the global reset signal and RST. RST may have
inversion if desired.
RCLK or one of the global clocks (CLK0 - CLK3). The selected signal can be
inverted if desired.
RCEN or one of the global clocks (CLK1 - CLK2). The selected signal can
be inverted if desired.
Created by the logical OR of the global reset signal and RST. RST may have
inversion if desired.
11

LC5256MC-5F256C PDF文件相关型号

LC5512MC-45F256C,LC5512MC-45F484C,LC5512MC-45Q208C,LC5512MC-75F256C,LC5512MC-75F484C,LC5768MC-5F484C,LC5768MC-75F484C

LC5256MC-5F256C 产品属性

  • Lattice

  • CPLD - 复杂可编程逻辑器件

  • EEPROM/SRAM

  • 256

  • 160

  • 300 MHz

  • 4 ns

  • 100

  • 1.8 V

  • 16 mA

  • + 90 C

  • 0 C

  • FPBGA-256-100

  • SMD/SMT

  • Tube

  • 450

  • 1.95 V

  • 1.65 V

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