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LC5256MC-5F256C Datasheet

  • LC5256MC-5F256C

  • Lattice Semiconductor [3.3V, 2.5V and 1.8V In-System Progra...

  • 427.20KB

  • LATTICE   LATTICE

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Lattice Semiconductor
Figure 15. PLL Block Diagram
ispXPLD 5000MX Family Data Sheet
CLK_IN
Input Clock
(M) Divider
Programable
Delay
PLL_RST
VCO
and
Phase
Detector
Post-scalar
(V) Divider
CLK_OUT
Clock Net
PLL_LOCK
Feedback
Loop
(N) Divider
PLL_FBK
Secondary
Clock
(K) Divider
SEC_OUT
Clock Net
Figure 16. Connection of Optional PLL Inputs and Outputs
To GRP
PLL_LOCK
CLK_OUT
From Macrocell
To GRP
PLL_RST
To GRP
From Macrocell
To GRP
PLL_FBK
I/O Pin*
From Macrocell
*See pinout table for details
I/O Pin*
I/O Pin*
In order to facilitate the multiply and divide capabilities of the PLL, each PLL has dividers associated with it: M, N
and K. The M divider is used to divide the clock signal, while the N divider is used to multiply the clock signal. The
K divider is only used when a secondary clock output is needed. This divider divides the primary clock output and
feeds to a separate global clock net. The V divider is used to provide lower frequency output clocks, while maintain-
ing a stable, high frequency output from the PLL鈥檚 VCO circuit. The PLL also has a delay feature that allows the out-
put clock to be advanced or delayed to improve set-up and clock-to-out times for better performance. For more
information on the PLL, please refer to Lattice technical note number TN1003,
Lattice sysCLOCK PLL Usage
Guidelines.
16

LC5256MC-5F256C PDF文件相关型号

LC5512MC-45F256C,LC5512MC-45F484C,LC5512MC-45Q208C,LC5512MC-75F256C,LC5512MC-75F484C,LC5768MC-5F484C,LC5768MC-75F484C

LC5256MC-5F256C 产品属性

  • Lattice

  • CPLD - 复杂可编程逻辑器件

  • EEPROM/SRAM

  • 256

  • 160

  • 300 MHz

  • 4 ns

  • 100

  • 1.8 V

  • 16 mA

  • + 90 C

  • 0 C

  • FPBGA-256-100

  • SMD/SMT

  • Tube

  • 450

  • 1.95 V

  • 1.65 V

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