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LC5256MC-5F256C Datasheet

  • LC5256MC-5F256C

  • Lattice Semiconductor [3.3V, 2.5V and 1.8V In-System Progra...

  • 427.20KB

  • LATTICE   LATTICE

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Lattice Semiconductor
Figure 1. ispXPLD 5000MX Block Diagram
PROGRAM
ispXPLD 5000MX Family Data Sheet
TDO
V
CCJ
GND
TMS
TCK
V
CC
ISP Port
V
CCO0
V
REF0
sysIO
Bank 0
OSA
TDI
V
CCO3
V
REF3
MFB
MFB
sysIO
Bank 3
OSA
MFB
GCLCK0
V
CCP
GNDP
GCLK1
sysIO
Bank 1
Optional
sysCONFIG
Interface
MFB
GCLCK3
Global
Routing
Pool
(GRP)
sysCLOCK
PLL 0
sysCLOCK
PLL 1
GCLK2
MFB
MFB
sysIO
Bank 2
RESET
GOE0
GOE1
V
REF2
V
CCO2
OSA
OSA
V
REF1
V
CCO1
MFB
MFB
Introduction
The ispXPLD 5000MX family represents a new class of device, referred to as the eXpanded Programmable Logic
Devices (XPLDs). These devices extend the capability of Lattice鈥檚 popular SuperWIDE ispMACH 5000 architecture
by providing 铿俥xible memory capability. The family supports single- or dual-port SRAM, FIFO, and ternary CAM
operation. Extra logic has also been included to allow ef铿乧ient implementation of arithmetic functions. In addition,
sysCLOCK PLLs and sysIO interfaces provide support for the system-level needs of designers.
The devices provide designers with a convenient one-chip solution that provides logic availability at boot-up, design
security, and extreme recon铿乬urability. The use of advanced process technology provides industry-leading perfor-
mance with combinatorial propagation delay as low as 4.0ns, 2.8ns clock-to-out delay, 2.2ns set-up time, and oper-
ating frequency up to 300MHz. This performance is coupled with low static and dynamic power consumption. The
ispXPLD 5000MX architecture provides predictable deterministic timing.
The availability of 3.3, 2.5 and 1.8V versions of these devices along with the 铿俥xibility of the sysIO interface helps
users meet the challenge of today鈥檚 mixed voltage designs. Inputs can be safely driven up to 5.5V when an I/O
bank is con铿乬ured for 3.3V operation, making this family 5V tolerant. Boundary scan testability further eases inte-
gration into today鈥檚 complex systems. A variety of density and package options increase the likelihood of a good 铿乼
for a particular application. Table 1 shows the members of the ispXPLD 5000MX family.
Architecture
The ispXPLD 5000MX devices consist of Multi-Function Blocks (MFBs) interconnected with a Global Routing Pool.
Signals enter and leave the device via one of four sysIO banks. Figure 1 shows the block diagram of the ispXPLD
2

LC5256MC-5F256C PDF文件相关型号

LC5512MC-45F256C,LC5512MC-45F484C,LC5512MC-45Q208C,LC5512MC-75F256C,LC5512MC-75F484C,LC5768MC-5F484C,LC5768MC-75F484C

LC5256MC-5F256C 产品属性

  • Lattice

  • CPLD - 复杂可编程逻辑器件

  • EEPROM/SRAM

  • 256

  • 160

  • 300 MHz

  • 4 ns

  • 100

  • 1.8 V

  • 16 mA

  • + 90 C

  • 0 C

  • FPBGA-256-100

  • SMD/SMT

  • Tube

  • 450

  • 1.95 V

  • 1.65 V

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