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LC5256MC-5F256C Datasheet

  • LC5256MC-5F256C

  • Lattice Semiconductor [3.3V, 2.5V and 1.8V In-System Progra...

  • 427.20KB

  • LATTICE   LATTICE

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Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MX Family Internal Switching Characteristics (Continued)
Over Recommended Operating Conditions
Parameter
t
CASC
t
CICOMFB
t
CICOMC
Description
Additional Delay for
PT Cascading
between MFBs
Carry Chain Delay,
MFB to MFB
Carry Chain Delay,
Macro-Cell to
Macro-Cell
Routing Delay for
Extended Function
Flags
Additional Flag
Delay when
Expanding Data
Widths
Counter Sum Delay
Block Loading
Adder
PT Expander Adder
Additional Delay for
the Input Register
Secondary PLL
Output Delay
MFB Input Extender
Input Buffer Selec-
tion Adder
Output Buffer
Selection Adder
Write Data Setup
before Write Clock
Time
Write Data Hold
after Write Clock
Time
Opposite Clock
Cycle Delay
Write Clock to Full
Flag Delay
Write Clock to
Almost Full Flag
Delay
Read Clock to
Empty Flag Delay
Read Clock to
Almost Empty Flag
Delay
Base
Parameter
鈥?/div>
鈥?/div>
鈥?/div>
-4
-45
-5
-52
-75
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
鈥?/div>
鈥?/div>
鈥?/div>
0.71
0.35
0.10
鈥?/div>
鈥?/div>
鈥?/div>
0.80
0.39
0.11
鈥?/div>
鈥?/div>
鈥?/div>
0.89
0.44
0.13
鈥?/div>
鈥?/div>
鈥?/div>
0.92
0.46
0.13
鈥?/div>
鈥?/div>
鈥?/div>
1.33
0.66
0.19
ns
ns
ns
t
FLAG
鈥?/div>
t
FLAGFULL
,
t
FLAGAFULL,
t
FLAGEMPTY
,
t
FLAGAEMPTY
t
PTSA
鈥?/div>
2.62
鈥?/div>
2.94
鈥?/div>
3.27
鈥?/div>
3.40
鈥?/div>
4.91
ns
t
FLAGEXP
t
SUM
鈥?/div>
鈥?/div>
2.57
0.80
鈥?/div>
鈥?/div>
2.89
0.90
鈥?/div>
鈥?/div>
3.21
1.00
鈥?/div>
鈥?/div>
3.34
1.04
鈥?/div>
鈥?/div>
4.82
1.50
ns
ns
Optional Adjusters
t
BLA
t
EXP
t
INDIO
t
PLL_SEC_DELAY
t
INEXP
t
ROUTE
t
ROUTE
t
INREG
t
PLL_DELAY
t
ROUTE
t
GCLK_IN,
t
IN,
t
GOE,
t
RST
t
BUF
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
0.04
0.53
0.50
0.91
0.62
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
0.04
0.60
0.56
0.91
0.70
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
0.05
0.66
0.63
0.91
0.78
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
0.05
0.69
0.65
0.91
0.81
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
0.07
0.99
0.94
0.91
1.16
ns
ns
ns
ns
ns
Input and Output Buffer Delays
t
IOI
t
IOO
FIFO
t
FIFOWCLKS
鈥?/div>
-0.27
鈥?/div>
-0.27
鈥?/div>
-0.22
鈥?/div>
-0.22
鈥?/div>
-0.21
鈥?/div>
ns
ns
Refer to sysIO Adjuster Tables
ns
t
FIFOWCLKH
t
FIFOCLKSKEW
t
FIFOFULL
t
FIFOAFULL
t
FIFOEMPTY
t
FIFOAEMPTY
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
-0.01
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
1.40
3.08
3.08
3.08
3.08
-0.01
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
1.40
3.08
3.08
3.08
3.08
-0.01
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
1.76
3.85
3.86
3.86
3.86
-0.01
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
1.76
3.85
3.86
3.86
3.86
-0.01
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
1.83
4.00
4.01
4.01
4.01
ns
ns
ns
ns
ns
ns
34

LC5256MC-5F256C PDF文件相关型号

LC5512MC-45F256C,LC5512MC-45F484C,LC5512MC-45Q208C,LC5512MC-75F256C,LC5512MC-75F484C,LC5768MC-5F484C,LC5768MC-75F484C

LC5256MC-5F256C 产品属性

  • Lattice

  • CPLD - 复杂可编程逻辑器件

  • EEPROM/SRAM

  • 256

  • 160

  • 300 MHz

  • 4 ns

  • 100

  • 1.8 V

  • 16 mA

  • + 90 C

  • 0 C

  • FPBGA-256-100

  • SMD/SMT

  • Tube

  • 450

  • 1.95 V

  • 1.65 V

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