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LC5256MC-5F256C Datasheet

  • LC5256MC-5F256C

  • Lattice Semiconductor [3.3V, 2.5V and 1.8V In-System Progra...

  • 427.20KB

  • LATTICE   LATTICE

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Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MX Family Internal Switching Characteristics (Continued)
Over Recommended Operating Conditions
Parameter
t
DPCEBS
Description
Clock Enable B
Setup before Clock
B Time
Clock Enable Hold
B after Clock B
Time
Address B Setup
before Clock B Time
Address B Hold
time after Clock B
Time
R/W B Setup before
Clock B Time
R/W B Hold time
after Clock B Time
Write Data B Setup
before Clock B Time
Write Data B Hold
after Clock B Time
Read Clock A to
Output Delay
Read Clock B to
Output Delay
Opposite Clock
Cycle Delay
Reset to RAM
Output Delay
Reset Recovery
Time
Reset Pulse Width
Base
Parameter
鈥?/div>
-4
-45
-5
-52
-75
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
2.33
鈥?/div>
2.33
鈥?/div>
2.33
鈥?/div>
2.33
鈥?/div>
3.03
鈥?/div>
ns
t
DPCEBH
t
DPADDBS
t
DPADDBH
t
DPRWBS
t
DPRWBH
t
DPDATABS
t
DPDATABH
t
DPRCLKAO
t
DPRCLKBO
t
DPCLKSKEW
t
DPRSTO
t
DPRSTR
t
DPRSTPW
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
-2.95
-0.27
-0.01
-0.27
-0.01
-0.27
-0.01
鈥?/div>
鈥?/div>
1.40
鈥?/div>
1.20
0.14
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
5.97
5.16
鈥?/div>
3.30
鈥?/div>
鈥?/div>
-2.95
-0.27
-0.01
-0.27
-0.01
-0.27
-0.01
鈥?/div>
鈥?/div>
1.40
鈥?/div>
1.20
0.14
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
5.92
5.16
鈥?/div>
3.30
鈥?/div>
鈥?/div>
-2.95
-0.27
-0.01
-0.27
-0.01
-0.27
-0.01
鈥?/div>
鈥?/div>
1.40
鈥?/div>
1.20
0.14
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
5.86
5.16
鈥?/div>
3.30
鈥?/div>
鈥?/div>
-2.95
-0.27
-0.01
-0.27
-0.01
-0.27
-0.01
鈥?/div>
鈥?/div>
1.40
鈥?/div>
1.20
0.14
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
5.65
5.16
鈥?/div>
3.30
鈥?/div>
鈥?/div>
-2.27
-0.21
-0.01
-0.21
-0.01
-0.21
-0.01
鈥?/div>
鈥?/div>
1.83
鈥?/div>
1.56
0.19
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
9.86
6.71
鈥?/div>
4.29
鈥?/div>
鈥?/div>
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Timing v.1.8
1. The PT-delay to clock of RAM/FIFO/CAM should be t
BCLK
instead of t
PTCLK.
2. The PT-delay to set/reset of RAM/FIFO/CAM should be t
BSR
instead of t
PTSR.
39

LC5256MC-5F256C PDF文件相关型号

LC5512MC-45F256C,LC5512MC-45F484C,LC5512MC-45Q208C,LC5512MC-75F256C,LC5512MC-75F484C,LC5768MC-5F484C,LC5768MC-75F484C

LC5256MC-5F256C 产品属性

  • Lattice

  • CPLD - 复杂可编程逻辑器件

  • EEPROM/SRAM

  • 256

  • 160

  • 300 MHz

  • 4 ns

  • 100

  • 1.8 V

  • 16 mA

  • + 90 C

  • 0 C

  • FPBGA-256-100

  • SMD/SMT

  • Tube

  • 450

  • 1.95 V

  • 1.65 V

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