Lattice Semiconductor
Cascading For Wide Operation
ispXPLD 5000MX Family Data Sheet
In several modes it is possible to cascade adjacent MFBs to support wider operation. Table 2 details the different
cascading options. There are chains of MFBs in each device which determine those MFBs that are adjacent for the
purposes of cascading. Table 3 indicates these chains. The ispXPLD 5000MX design tools automatically cascade
blocks if required by a particular design.
Table 2. Cascading Modes For Wide Support
Mode
Logic
FIFO
CAM
Cascading Function
Input Width.
Allows two MFBs to act as a 136-input block.
Arithmetic.
Allow the carry chain to pass between two MFBs.
Memory Width Expansion.
Allows MFBs to be cascaded for greater width support.
Memory Width Expansion.
Allows up to four MFBs to be cascaded for greater width support.
Table 3. MFB Cascade Chain
Device
ispXPLD 5256MX
ispXPLD 5512MX
ispXPLD 5768MX
ispXPLD 51024MX
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MFBs in Cascade Chain
SuperWIDE Logic Mode
In logic mode, each MFB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic
product terms and four control product terms. The MFB has 68 inputs from the Global Routing Pool, which are
available in both true and complement form for every product term. It is also possible to cascade adjacent MFBs to
create a block with 136 inputs. The four control product terms are used for shared reset, clock, clock enable, and
output enable functions. Figure 3 shows the overall structure of the MFB in logic mode while Figure 4 provides a
more detailed view from the perspective of a macrocell slice.
4
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LC5256MC-5F256C PDF文件相关型号
LC5512MC-45F256C,LC5512MC-45F484C,LC5512MC-45Q208C,LC5512MC-75F256C,LC5512MC-75F484C,LC5768MC-5F484C,LC5768MC-75F484C
LC5256MC-5F256C 产品属性
Lattice
CPLD - 复杂可编程逻辑器件
EEPROM/SRAM
256
160
300 MHz
4 ns
100
1.8 V
16 mA
+ 90 C
0 C
FPBGA-256-100
SMD/SMT
Tube
450
1.95 V
1.65 V
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