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LC5256MC-5F256C Datasheet

  • LC5256MC-5F256C

  • Lattice Semiconductor [3.3V, 2.5V and 1.8V In-System Progra...

  • 427.20KB

  • LATTICE   LATTICE

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Lattice Semiconductor
AND-Array
ispXPLD 5000MX Family Data Sheet
The programmable AND-Array consists of 68 inputs and 164 output product terms. The 68 inputs from the GRP are
used to form 136 lines in the AND-Array (true and complement of the inputs). Each line in the array can be con-
nected to any of the 164 output product terms via a wired AND. Each of the 160 logic product terms feed the Dual-
OR Array with the remaining four control product terms feeding the Shared PT Clock, Shared PT Clock Enable,
Shared PT Reset and Shared PT OE. Starting with PT0 sets of 铿乿e product terms form product term clusters.
There is one product term cluster for every macrocell in the MFB. In addition to the four control product terms, the
铿乺st, third, fourth and 铿乫th product terms of each cluster can be used as a PTOE, PT Clock, PT Preset and PT
Reset, respectively. Figure 5 is a graphical representation of the AND-Array.
Figure 5. AND Array
In[0]
In[66]
In[67]
PT0
PT1
PT2
PT3
PT4
Cluster 0
PT155
PT156
PT157
Cluster 31
PT158
PT159
PT160 Shared clock enable
PT161 Shared clock
PT162 Shared reset
PT163 Shared OE
Note:
Indicates programmable fuse.
Dual-OR Array (Including Arithmetic Support)
The Dual-OR Array consists of 64 OR gates. There are two OR gates per macrocell in the MFB. These OR gates
are referred to as the Expandable PTSA OR gate and the PTSA-Bypass OR gate. The PTSA-Bypass OR gate
receives its 铿乿e inputs from the combination of product terms associated with the product term cluster. The PTSA-
Bypass OR gate feeds the macrocell directly for fast narrow logic. The Expandable PTSA OR gate receives 铿乿e
inputs from the combination of product terms associated with the product term cluster. It also receives an additional
input from the Expanded PTSA OR gate of the N-7 macrocell, where N is the number of the macrocell associated
with the current OR gate. The Expandable PTSA OR gate feeds the PTSA for sharing with other product terms and
the N+7 Expandable PTSA OR gate. This allows cascading of multiple OR gates for wide functions. There is a
small timing adder for each level of expansion. Figure 6 is a graphical representation of the Dual-OR Array.
The Dual-OR PT sharing array also contains logic to aid in the ef铿乧ient implementation of arithmetic functions. This
logic takes Carry In and allows the generation of Carry Out along with a SUM signal. Subtractors can be imple-
mented using the two鈥檚 complement method. Carry is propagated from macrocells 0 to macrocell 31. Macrocell
zero can have its carry input connected to the carry output of macrocell 31 in an adjacent MFB or it can be set to
zero or one. If a macrocell is not used in an arithmetic function carry can bypass it. The carry chain 铿俹ws is the
same as that for PT cascading.
6

LC5256MC-5F256C PDF文件相关型号

LC5512MC-45F256C,LC5512MC-45F484C,LC5512MC-45Q208C,LC5512MC-75F256C,LC5512MC-75F484C,LC5768MC-5F484C,LC5768MC-75F484C

LC5256MC-5F256C 产品属性

  • Lattice

  • CPLD - 复杂可编程逻辑器件

  • EEPROM/SRAM

  • 256

  • 160

  • 300 MHz

  • 4 ns

  • 100

  • 1.8 V

  • 16 mA

  • + 90 C

  • 0 C

  • FPBGA-256-100

  • SMD/SMT

  • Tube

  • 450

  • 1.95 V

  • 1.65 V

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