鈮?/div>
1 [ms] (Logic block power supply voltage V
DD
fall time)
Figure 3
鈥?1/4 duty
t1 t2
VDD
VDET
VDET
t3 t4
VLCD
CE
D1 to D76
S0, S1, K0, K1
P0 to P3, SC, DR, DT
Display and control data transfer
Undefined
Defined
Undefined
VIL
Internal data
Internal data (D77 to D152)
Internal data (D153 to D228)
Internal data (D229 to D300)
Undefined
Defined
Undefined
Undefined
Defined
Undefined
Undefined
System reset period
Defined
Undefined
Note: t1
鈮?/div>
1 [ms] (Logic block power supply voltage V
DD
rise time)
t2
鈮?/div>
0
t3
鈮?/div>
0
t4
鈮?/div>
1 [ms] (Logic block power supply voltage V
DD
fall time)
Figure 4
No. 6266-24/37
prev
next