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MSP430F155IRTDR Datasheet

  • MSP430F155IRTDR

  • Texas Instruments [MIXED SIGNAL MICROCONTROLLER]

  • 1248.35KB

  • TI

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MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368E 鈭?OCTOBER 2002 鈭?REVISED AUGUST 2006
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh 鈭?0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE
Power-up
External Reset
Watchdog
Flash memory
NMI
Oscillator Fault
Flash memory access violation
Timer_B7 (see Note 5)
INTERRUPT FLAG
WDTIFG
KEYV
(see Note 1)
NMIIFG (see Notes 1 & 3)
OFIFG (see Notes 1 & 3)
ACCVIFG (see Notes 1 & 3)
TBCCR0 CCIFG
(see Note 2)
TBCCR1 to TBCCR6
CCIFGs, TBIFG
(see Notes 1 & 2)
CAIFG
WDTIFG
URXIFG0
UTXIFG0
I2CIFG (see Note 4)
ADC12IFG
(see Notes 1 & 2)
TACCR0 CCIFG
(see Note 2)
TACCR1 and TACCR2
CCIFGs, TAIFG
(see Notes 1 & 2)
P1IFG.0 to P1IFG.7
(see Notes 1 & 2)
URXIFG1
UTXIFG1
P2IFG.0 to P2IFG.7
(see Notes 1 & 2)
DAC12_0IFG,
DAC12_1IFG
DMA0IFG, DMA1IFG,
DMA2IFG (see Notes 1 & 2)
SYSTEM INTERRUPT
Reset
WORD ADDRESS
0FFFEh
PRIORITY
15, highest
(Non)maskable
(Non)maskable
(Non)maskable
Maskable
0FFFCh
0FFFAh
14
13
Timer_B7 (see Note 5)
Comparator_A
Watchdog timer
USART0 receive
I
2
C
USART0 transmit
transmit/receive/others
ADC12
Timer_A3
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
0FFF8h
0FFF6h
0FFF4h
0FFF2h
0FFF0h
0FFEEh
0FFECh
12
11
10
9
8
7
6
Timer_A3
Maskable
0FFEAh
5
I/O port P1 (eight flags)
USART1 receive
USART1 transmit
I/O port P2 (eight flags)
DAC12
DMA
Maskable
Maskable
Maskable
Maskable
Maskable
0FFE8h
0FFE6h
0FFE4h
0FFE2h
0FFE0h
4
3
2
1
0, lowest
NOTES: 1.
2.
3.
4.
5.
Multiple source flags
Interrupt flags are located in the module.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
I
2
C interrupt flags located in the module
Timer_B7 in MSP430x16x/161x family has 7 CCRs; Timer_B3 in MSP430x15x family has 3 CCRs; in Timer_B3 there are only
interrupt flags TBCCR0, 1 and 2 CCIFGs and the interrupt-enable bits TBCCR0, 1 and 2 CCIEs.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
11

MSP430F155IRTDR PDF文件相关型号

MSP430F167IRTDR,MSP430X15X_08

MSP430F155IRTDR 产品属性

  • The Ultra-Low Power MSP430MSP430 OverviewMSP430 Design ToolsMSP430 PeripheralsMSP430x2xx/4xx and Wireless OverviewPortable Medical Solutions with MSP430MSP430 for Utility Metering SolutionsMSP430: How to JTAGMSP430, How To Use the Clock SystemGrace Software Graphical User InterfaceMCU OverviewDriver LibraryMSP430Ware Overview

  • 2,500

  • 集成电路 (IC)

  • 嵌入式 - 微控制器，

  • MSP430x1xx

  • RISC

  • 16-位

  • 8MHz

  • I²C，SPI，UART/USART

  • 欠压检测/复位，DMA，POR，PWM，WDT

  • 48

  • 16KB（16K x 8 + 256B）

  • 闪存

  • -

  • 512 x 8

  • 1.8 V ~ 3.6 V

  • A/D 8x12b，D/A 2x12b

  • 内部

  • -40°C ~ 85°C

  • 64-VFQFN 裸露焊盘

  • 带卷 (TR)

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