MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504A 鈭?JULY 2006 鈭?REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART Mode)
PARAMETER
fUSCI
fBITCLK
t
蟿
USCI input clock frequency
BITCLK clock frequency
(equals Baudrate in MBaud)
UART receive deglitch time
(see Note 1)
TEST CONDITIONS
Internal: SMCLK, ACLK
External: UCLK
Duty Cycle = 50%
卤
10%
2.2V /3 V
2.2 V
3V
50
50
150
100
VCC
MIN
TYP
MAX
UNIT
MHz
fSYSTEM
1
600
600
MHz
ns
ns
NOTES: 1. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode, see Figure 20 and Figure 21)
PARAMETER
fUSCI
tSU,MI
tHD,MI
tVALID,MO
USCI input clock frequency
SOMI input data setup time
SOMI input data hold time
SIMO output data valid time
UCLK edge to SIMO valid;
CL = 20 pF
TEST CONDITIONS
SMCLK, ACLK
Duty Cycle = 50%
卤
10%
2.2 V
3V
2.2 V
3V
2.2 V
3V
110
75
0
0
30
20
VCC
MIN
TYP
MAX
UNIT
MHz
ns
ns
ns
ns
ns
ns
fSYSTEM
USCI (SPI Slave Mode, see Figure 22 and Figure 23)
PARAMETER
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
tSU,SI
tHD,SI
tVALID,SO
STE lead time
STE low to clock
STE lag time
Last clock to STE high
STE access time
STE low to SOMI data out
STE disable time
STE high to SOMI high impedance
SIMO input data setup time
SIMO input data hold time
SOMI output data valid time
UCLK edge to SOMI valid;
CL = 20 pF
TEST CONDITIONS
VCC
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V
3V
2.2 V
3V
2.2 V
3V
20
15
10
10
75
50
110
75
10
50
50
MIN
TYP
50
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
42
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
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