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SI5310 Datasheet

  • SI5310

  • Silicon Laboratories [PRECISION CLOCK MULTIPLIER/REGENERATO...

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Si5310
4. Functional Description
The Si5310 is an integrated clock multiplier and clock
regenerator device based on SIlicon Laboratories
DSPLL鈩?technology. The DSPLL phase locks to the
clock input signal (CLKIN) and generates a phase-
locked output clock (MULTOUT) at a multiple of the
input clock frequency. The DSPLL is also employed to
regenerate an output clock (CLKOUT) that is a jitter-
attenuated version of the input clock with clean rising
and falling edges.
The MULTOUT output is configured to operate in either
the 150鈥?67 MHz or the 600鈥?68 MHz frequency range
using the MULTSEL control input. A reference clock
input signal (REFCLK) is used by the DSPLL as a
reference for determination of the PLL lock status. For
convenience, REFCLK can be provided at any one of
five frequencies, each a multiple of the CLKIN
frequency. The REFCLK rate is automatically detected,
so no control inputs are needed for configuration. The
REFCLK input can be synchronous or asynchronous
with respect to the CLKIN input. The operating ranges
for the CLKIN, CLKOUT, MULTOUT, and REFCLK
signals are indicated in Table 9. Typical values for
several applications are presented in Table 10.
Table 9. CLKIN, CLKOUT, MULTOUT, REFCLK Operating Ranges
MULTSEL
CLKIN Range
(MHz)
REFCLK = 2
n
x CLKIN
卤100 ppm
(See Note 1)
n = 鈥?, 鈥?, 0, 1, 2
n = 鈥?, 鈥?, 鈥?, 0, 1
n = 鈥?, 鈥?, 鈥?, 鈥?, 0
n = 鈥?, 鈥?, 鈥?, 鈥?, 鈥?
n = 鈥?, 鈥?, 鈥?, 鈥?, 鈥?
n = 0, 1, 2, 3, 4
n = 鈥?, 0, 1, 2, 3
n = 鈥?, 鈥?, 0, 1, 2
n = 鈥?, 鈥?, 鈥?, 0, 1
n = 鈥?, 鈥?, 鈥?, 鈥?, 0
CLKOUT
MULTOUT
37.500鈥?1.750
75.000鈥?3.500
0
(MULTOUT = 600鈥?68 MHz)
150.000鈥?67.000
300.000鈥?34.000
600.000鈥?68.000
9.375鈥?0.438
18.750鈥?0.875
1
(MULTOUT = 150鈥?67 MHz)
37.500鈥?1.750
75.000鈥?3.500
150.000鈥?67.000
1xCLKIN
1xCLKIN
1xCLKIN
1xCLKIN
See Note 2
1xCLKIN
1xCLKIN
1xCLKIN
1xCLKIN
See Note 2
16xCLKIN
8xCLKIN
4xCLKIN
2xCLKIN
1xCLKIN
16xCLKIN
8xCLKIN
4xCLKIN
2xCLKIN
1xCLKIN
Note:
1.
The REFCLK input can be set to any one of the five CLKIN multiples indicated. The REFCLK input can be
asynchronous to the CLKIN input, but must be within 卤100 ppm of the stated CLKIN multiple.
2.
The CLKOUT output is not valid for MULTOUT:CLKIN ratios of 1:1 (MULTOUT = 1 x CLKIN.)
12
Rev. 1.2

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