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SI5310 Datasheet

  • SI5310

  • Silicon Laboratories [PRECISION CLOCK MULTIPLIER/REGENERATO...

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  • SILABS

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Si5310
5. Pin Descriptions: Si5310
MULTOUT+
MULTOUT鈥?/div>
MULTSEL
20 19 18
REXT
VDD
GND
REFCLK+
REFCLK鈥?/div>
GND
NC
17 16
15
PWRDN
14
VDD
1
2
3
4
5
6
LOL
GND
Pad
13
CLKOUT+
12
CLKOUT鈥?/div>
11
VDD
7
VDD
8
GND
9
CLKIN+
10
CLKIN鈥?/div>
Top View
Figure 11. Si5310 Pin Configuration
Table 11. Si5310 Pin Descriptions
Pin #
1
Pin Name
REXT
I/O
Signal Level
Description
External Bias Resistor.
This resistor is used by onboard circuitry to establish
bias currents within the device. This pin must be
connected to GND through a 10 k鈩?/div>
(1%)
resistor.
2.5 V
GND
Supply Voltage.
Nominally 2.5 V.
Supply Ground.
Nominally 0.0 V. The GND pad found on the bottom
of the 20-pin micro leaded package (see Figure 12)
must be connected directly to supply ground.
Differential Reference Clock.
The reference clock sets the initial operating fre-
quency used by the onboard PLL for clock regenera-
tion and multiplication. Additionally, the reference
clock is used as a reference in generation of the LOL
output and to bound the frequency drift of MULTOUT
when CLKIN is not present.
Loss of Lock.
This output is driven high when a divided version of
the clock multiplier output deviates from the refer-
ence clock frequency by the amount specified in
Table 4 on page 8.
Differential Clock Input.
Differential input clock from which MULTOUT is
derived.
2, 7, 11, 14
3, 8, 18, and
GND Pad
VDD
GND
4, 5
REFCLK+, REF-
CLK鈥?/div>
I
See Table 2
6
LOL
O
LVTTL
9, 10
CLKIN+, CLKIN鈥?/div>
I
See Table 2
Rev. 1.2
19

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